diff options
| author | Francisco Jerez <[email protected]> | 2016-01-14 12:17:01 -0800 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-02-08 15:47:21 -0800 |
| commit | 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 (patch) | |
| tree | 665103a85d9723947dec6d41162ca76d3927d252 /src | |
| parent | 0aa4f99f562a05880a779707cbcd46be459863bf (diff) | |
i965: Invalidate state cache before L3 partitioning set-up.
The state cache is also L3-backed so it seems sensible to make sure
it's clean as we do for other RO caches before repartitioning the L3.
This wasn't part of my original L3 partitioning code because I was
able to reproduce hangs on Gen7 hardware when the state cache
invalidation happened asynchronously with previous 3D rendering, which
should no longer be possible after the previous change.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 85f18d0e012..ff67c90fe87 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -355,6 +355,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg) PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_INSTRUCTION_INVALIDATE | + PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_NO_WRITE); /* Now send a third stalling flush to make sure that invalidation is |