r600g: use tables with ISA info v3

v3: added some flags including condition codes for ALU,
    fixed issue with CF reverse lookup (overlapping ranges of CF_ALU_xxx
    and other CF instructions)
    rebased on current master

Signed-off-by: Vadim Girlin <[email protected]>

10 files changed, 2378 insertions, 1789 deletions

diff --git a/src/gallium/drivers/r600/Makefile.sources b/src/gallium/drivers/r600/Makefile.sources
index 0885ae5ce1f..a99ef110d0c 100644
--- a/src/gallium/drivers/r600/Makefile.sources
+++ b/src/gallium/drivers/r600/Makefile.sources
@@ -3,6 +3,7 @@ C_SOURCES = \
 	r600_blit.c \
 	r600_buffer.c \
 	r600_hw_context.c \
+	r600_isa.c \
 	r600_pipe.c \
 	r600_query.c \
 	r600_resource.c \
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index 0dc3ffdaa38..fffc436e823 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -32,121 +32,94 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
 {
 	unsigned id = cf->id;
 
-	switch (cf->inst) {
-	case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-	case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-	case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-	case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-		/* prepend ALU_EXTENDED if we need more than 2 kcache sets */
-		if (cf->eg_alu_extended) {
-			bc->bytecode[id++] =
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE0(V_SQ_CF_INDEX_NONE) |
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE1(V_SQ_CF_INDEX_NONE) |
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE2(V_SQ_CF_INDEX_NONE) |
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE3(V_SQ_CF_INDEX_NONE) |
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK2(cf->kcache[2].bank) |
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK3(cf->kcache[3].bank) |
-				S_SQ_CF_ALU_WORD0_EXT_KCACHE_MODE2(cf->kcache[2].mode);
-			bc->bytecode[id++] = EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED |
-				S_SQ_CF_ALU_WORD1_EXT_KCACHE_MODE3(cf->kcache[3].mode) |
-				S_SQ_CF_ALU_WORD1_EXT_KCACHE_ADDR2(cf->kcache[2].addr) |
-				S_SQ_CF_ALU_WORD1_EXT_KCACHE_ADDR3(cf->kcache[3].addr) |
-				S_SQ_CF_ALU_WORD1_EXT_BARRIER(1);
-		}
+	if (cf->op == CF_NATIVE) {
+		bc->bytecode[id++] = cf->isa[0];
+		bc->bytecode[id++] = cf->isa[1];
+	} else {
+		const struct cf_op_info *cfop = r600_isa_cf(cf->op);
+		unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
+		if (cfop->flags & CF_ALU) { /* ALU clauses */
 
-		bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
-			S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
-			S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
-			S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
-		bc->bytecode[id++] = cf->inst |
-			S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
-			S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
-			S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
+			/* prepend ALU_EXTENDED if we need more than 2 kcache sets */
+			if (cf->eg_alu_extended) {
+				bc->bytecode[id++] =
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE0(V_SQ_CF_INDEX_NONE) |
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE1(V_SQ_CF_INDEX_NONE) |
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE2(V_SQ_CF_INDEX_NONE) |
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE3(V_SQ_CF_INDEX_NONE) |
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK2(cf->kcache[2].bank) |
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK3(cf->kcache[3].bank) |
+						S_SQ_CF_ALU_WORD0_EXT_KCACHE_MODE2(cf->kcache[2].mode);
+				bc->bytecode[id++] =
+						S_SQ_CF_ALU_WORD1_EXT_CF_INST(
+							r600_isa_cf_opcode(bc->isa->hw_class, CF_OP_ALU_EXT)) |
+						S_SQ_CF_ALU_WORD1_EXT_KCACHE_MODE3(cf->kcache[3].mode) |
+						S_SQ_CF_ALU_WORD1_EXT_KCACHE_ADDR2(cf->kcache[2].addr) |
+						S_SQ_CF_ALU_WORD1_EXT_KCACHE_ADDR3(cf->kcache[3].addr) |
+						S_SQ_CF_ALU_WORD1_EXT_BARRIER(1);
+			}
+			bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
+					S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
+					S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
+					S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
+			bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
+					S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
+					S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
+					S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
 					S_SQ_CF_ALU_WORD1_BARRIER(1) |
 					S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
-		break;
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
-		bc->bytecode[id++] = cf->inst |
+		} else if (cfop->flags & CF_CLAUSE) {
+			/* CF_TEX/VTX (CF_ALU already handled above) */
+			bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
+			bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
 					S_SQ_CF_WORD1_BARRIER(1) |
 					S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
-		break;
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
-			S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
-			S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
-			S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
-		bc->bytecode[id] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
-			cf->output.inst;
-		if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
-			bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
-		id++;
-		break;
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
-	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
-		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
-			S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
-			S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
-			S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
-		bc->bytecode[id] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
-			cf->output.inst |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) |
-			S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size);
-		if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
-			bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
-		id++;
-		break;
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-	case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
-	case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
-		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
-		bc->bytecode[id++] = cf->inst |
+		} else if (cfop->flags & CF_EXP) {
+			/* EXPORT instructions */
+			bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
+					S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
+					S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
+					S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
+			bc->bytecode[id] =
+					S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode);
+
+			if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
+				bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
+			id++;
+		} else if (cfop->flags & CF_STRM) {
+			/* MEM_STREAM instructions */
+			bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
+					S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
+					S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
+					S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
+			bc->bytecode[id] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) |
+					S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size);
+			if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
+				bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
+			id++;
+		} else {
+			/* branch, loop, call, return instructions */
+			bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
+			bc->bytecode[id++] =  S_SQ_CF_WORD1_CF_INST(opcode)|
 					S_SQ_CF_WORD1_BARRIER(1) |
 					S_SQ_CF_WORD1_COND(cf->cond) |
 					S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
-		break;
-	case CF_NATIVE:
-		bc->bytecode[id++] = cf->isa[0];
-		bc->bytecode[id++] = cf->isa[1];
-		break;
-	default:
-		R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
-		return -EINVAL;
+		}
 	}
 	return 0;
 }
 
-void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
+void eg_bytecode_export_read(struct r600_bytecode *bc,
+		struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
 {
 	output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
 	output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
@@ -159,7 +132,8 @@ void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0
 	output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
 	output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
 	output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
-	output->inst = EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
+	output->op = r600_isa_cf_by_opcode(bc->isa,
+			G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), /* is_cf_alu = */ 0 );
 	output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
 	output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
 	output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 1a501f62cba..6b60529f060 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -34,184 +34,14 @@
 #define NUM_OF_CYCLES 3
 #define NUM_OF_COMPONENTS 4
 
-static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+static inline unsigned int r600_bytecode_get_num_operands(
+		struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	if(alu->is_op3)
-		return 3;
-
-	switch (bc->chip_class) {
-	default:
-	case R600:
-	case R700:
-		switch (alu->inst) {
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
-			return 0;
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
-			return 2;
-
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
-		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
-			return 1;
-		default: R600_ERR(
-			"Need instruction operand number for 0x%x.\n", alu->inst);
-		}
-		break;
-	case EVERGREEN:
-	case CAYMAN:
-		switch (alu->inst) {
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
-			return 0;
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
-			return 2;
-
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
-		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
-			return 1;
-		default:
-			R600_ERR("Need instruction operand number for 0x%x.\n", alu->inst);
-		}
-		break;
-	}
-
-	return 3;
+	return r600_isa_alu(alu->op)->src_count;
 }
 
-int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
+int r700_bytecode_alu_build(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu, unsigned id);
 
 static struct r600_bytecode_cf *r600_bytecode_cf(void)
 {
@@ -298,16 +128,17 @@ static int r600_bytecode_add_cf(struct r600_bytecode *bc)
 	return 0;
 }
 
-int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
+int r600_bytecode_add_output(struct r600_bytecode *bc,
+		const struct r600_bytecode_output *output)
 {
 	int r;
 
 	if (output->gpr >= bc->ngpr)
 		bc->ngpr = output->gpr + 1;
 
-	if (bc->cf_last && (bc->cf_last->inst == output->inst ||
-		(bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
-		output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
+	if (bc->cf_last && (bc->cf_last->op == output->op ||
+		(bc->cf_last->op == CF_OP_EXPORT &&
+		output->op == CF_OP_EXPORT_DONE)) &&
 		output->type == bc->cf_last->output.type &&
 		output->elem_size == bc->cf_last->output.elem_size &&
 		output->swizzle_x == bc->cf_last->output.swizzle_x &&
@@ -320,7 +151,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
 			(output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
 
 			bc->cf_last->output.end_of_program |= output->end_of_program;
-			bc->cf_last->output.inst = output->inst;
+			bc->cf_last->op = bc->cf_last->output.op = output->op;
 			bc->cf_last->output.gpr = output->gpr;
 			bc->cf_last->output.array_base = output->array_base;
 			bc->cf_last->output.burst_count += output->burst_count;
@@ -330,7 +161,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
 			output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
 
 			bc->cf_last->output.end_of_program |= output->end_of_program;
-			bc->cf_last->output.inst = output->inst;
+			bc->cf_last->op = bc->cf_last->output.op = output->op;
 			bc->cf_last->output.burst_count += output->burst_count;
 			return 0;
 		}
@@ -339,7 +170,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
 	r = r600_bytecode_add_cf(bc);
 	if (r)
 		return r;
-	bc->cf_last->inst = output->inst;
+	bc->cf_last->op = output->op;
 	memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
 	return 0;
 }
@@ -347,137 +178,18 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
 /* alu instructions that can ony exits once per group */
 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	switch (bc->chip_class) {
-	case R600:
-	case R700:
-		return !alu->is_op3 && (
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
-	case EVERGREEN:
-	case CAYMAN:
-	default:
-		return !alu->is_op3 && (
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
-	}
+	return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
 }
 
 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	switch (bc->chip_class) {
-	case R600:
-	case R700:
-		return !alu->is_op3 && (
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
-	case EVERGREEN:
-	case CAYMAN:
-	default:
-		return !alu->is_op3 && (
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
-	}
-}
-
-static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
-{
-	switch (bc->chip_class) {
-	case R600:
-	case R700:
-		return !alu->is_op3 &&
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
-	case EVERGREEN:
-	case CAYMAN:
-	default:
-		return !alu->is_op3 &&
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
-	}
+	return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
+			(r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
 }
 
 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	switch (bc->chip_class) {
-	case R600:
-	case R700:
-		return !alu->is_op3 && (
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
-			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
-	case EVERGREEN:
-	case CAYMAN:
-	default:
-		return !alu->is_op3 && (
-			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
-	}
+	return r600_isa_alu(alu->op)->flags & AF_MOVA;
 }
 
 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
@@ -497,130 +209,28 @@ static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 	return 0;
 }
 
-static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
-{
-	return min <= opcode && opcode <= max;
-}
-
-/* ALU instructions that can only execute on the vector unit:
- *
- * opcode ranges:
- * R6xx/R7xx:
- *   op3 : [0x08 - 0x0B]
- *   op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
- *
- * EVERGREEN:
- *   op3: [0x04 - 0x11]
- *   op2: [0xA0 - 0xE2]
- */
 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	switch (bc->chip_class) {
-	case R600:
-	case R700:
-		if (alu->is_op3)
-			return is_opcode_in_range(alu->inst,
-					V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
-					V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
-		else
-			return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
-					is_opcode_in_range(alu->inst,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
-					is_opcode_in_range(alu->inst,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
-					is_opcode_in_range(alu->inst,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
-					is_opcode_in_range(alu->inst,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
-
-	case EVERGREEN:
-		if (alu->is_op3)
-			return is_opcode_in_range(alu->inst,
-					EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
-					EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
-		else
-			return is_opcode_in_range(alu->inst,
-					EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
-					EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
-	case CAYMAN:
-	default:
-		assert(0);
-		return 0;
-	}
+	unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
+	return !(slots & AF_S);
 }
 
-/* ALU instructions that can only execute on the trans unit:
- *
- * opcode ranges:
- * R600:
- *   op3: 0x0C
- *   op2: [0x60 - 0x79]
- *
- * R700:
- *   op3: 0x0C
- *   op2: [0x60 - 0x6F], [0x73 - 0x79]
- *
- * EVERGREEN:
- *   op3: 0x1F
- *   op2: [0x81 - 0x9C]
- */
 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-
-	switch (bc->chip_class) {
-	case R600:
-		if (alu->is_op3)
-			return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
-		else
-			return is_opcode_in_range(alu->inst,
-					V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
-					V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
-	case R700:
-		if (alu->is_op3)
-			return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
-		else
-			return is_opcode_in_range(alu->inst,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
-						V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
-					is_opcode_in_range(alu->inst,
-							V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
-							V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
-	case EVERGREEN:
-		if (alu->is_op3)
-			return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
-		else
-			return is_opcode_in_range(alu->inst,
-					EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
-					EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
-	case CAYMAN:
-	default:
-		assert(0);
-		return 0;
-	}
+	unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
+	return !(slots & AF_V);
 }
 
 /* alu instructions that can execute on any unit */
 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	return !is_alu_vec_unit_inst(bc, alu) &&
-		!is_alu_trans_unit_inst(bc, alu);
+	unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
+	return slots == AF_VS;
 }
 
 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
 {
-	switch (bc->chip_class) {
-	case R600:
-	case R700:
-		return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
-	case EVERGREEN:
-	case CAYMAN:
-	default:
-		return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
-	}
+	return alu->op == ALU_OP0_NOP;
 }		
 
 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
@@ -929,7 +539,7 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
 		if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
 			gpr[i] = prev[i]->dst.sel;
 			/* cube writes more than PV.X */
-			if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
+			if (is_alu_reduction_inst(bc, prev[i]))
 				chan[i] = 0;
 			else
 				chan[i] = prev[i]->dst.chan;
@@ -1351,7 +961,9 @@ static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
 	return 0;
 }
 
-static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
+static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu,
+		unsigned type)
 {
 	struct r600_bytecode_kcache kcache_sets[4];
 	struct r600_bytecode_kcache *kcache = kcache_sets;
@@ -1364,7 +976,7 @@ static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r60
 		if ((r = r600_bytecode_add_cf(bc))) {
 			return r;
 		}
-		bc->cf_last->inst = type;
+		bc->cf_last->op = type;
 
 		/* retry with the new clause */
 		kcache = bc->cf_last->kcache;
@@ -1394,7 +1006,7 @@ static int insert_nop_r6xx(struct r600_bytecode *bc)
 
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+		alu.op = ALU_OP0_NOP;
 		alu.src[0].chan = i;
 		alu.dst.chan = i;
 		alu.last = (i == 3);
@@ -1419,7 +1031,7 @@ static int load_ar_r6xx(struct r600_bytecode *bc)
 		bc->force_add_cf = 1;
 
 	memset(&alu, 0, sizeof(alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
+	alu.op = ALU_OP1_MOVA_GPR_INT;
 	alu.src[0].sel = bc->ar_reg;
 	alu.src[0].chan = bc->ar_chan;
 	alu.last = 1;
@@ -1450,7 +1062,7 @@ static int load_ar(struct r600_bytecode *bc)
 		bc->force_add_cf = 1;
 
 	memset(&alu, 0, sizeof(alu));
-	alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
+	alu.op = ALU_OP1_MOVA_INT;
 	alu.src[0].sel = bc->ar_reg;
 	alu.src[0].chan = bc->ar_chan;
 	alu.last = 1;
@@ -1463,7 +1075,8 @@ static int load_ar(struct r600_bytecode *bc)
 	return 0;
 }
 
-int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
+int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
+		const struct r600_bytecode_alu *alu, unsigned type)
 {
 	struct r600_bytecode_alu *nalu = r600_bytecode_alu();
 	struct r600_bytecode_alu *lalu;
@@ -1473,10 +1086,10 @@ int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytec
 		return -ENOMEM;
 	memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
 
-	if (bc->cf_last != NULL && bc->cf_last->inst != type) {
+	if (bc->cf_last != NULL && bc->cf_last->op != type) {
 		/* check if we could add it anyway */
-		if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
-			type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
+		if (bc->cf_last->op == CF_OP_ALU &&
+			type == CF_OP_ALU_PUSH_BEFORE) {
 			LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
 				if (lalu->execute_mask) {
 					bc->force_add_cf = 1;
@@ -1495,7 +1108,7 @@ int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytec
 			return r;
 		}
 	}
-	bc->cf_last->inst = type;
+	bc->cf_last->op = type;
 
 	/* Check AR usage and load it if required */
 	for (i = 0; i < 3; i++)
@@ -1586,7 +1199,7 @@ int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytec
 
 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
 {
-	return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
+	return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
 }
 
 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
@@ -1608,19 +1221,9 @@ static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_byt
 
 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
 {
-	switch (bc->chip_class) {
-	case R700:
-	case R600:
-		return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
-		       bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
-	case EVERGREEN:
-		return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
-	case CAYMAN:
-		return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
-	default:
-		R600_ERR("Unknown chip class %d.\n", bc->chip_class);
-		return FALSE;
-	}
+	return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
+			(bc->chip_class == CAYMAN ||
+			bc->cf_last->op != CF_OP_TEX));
 }
 
 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
@@ -1644,13 +1247,11 @@ int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_v
 		switch (bc->chip_class) {
 		case R600:
 		case R700:
-			bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
-			break;
 		case EVERGREEN:
-			bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
+			bc->cf_last->op = CF_OP_VTX;
 			break;
 		case CAYMAN:
-			bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
+			bc->cf_last->op = CF_OP_TEX;
 			break;
 		default:
 			R600_ERR("Unknown chip class %d.\n", bc->chip_class);
@@ -1682,7 +1283,7 @@ int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_t
 
 	/* we can't fetch data und use it as texture lookup address in the same TEX clause */
 	if (bc->cf_last != NULL &&
-		bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
+		bc->cf_last->op == CF_OP_TEX) {
 		struct r600_bytecode_tex *ttex;
 		LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
 			if (ttex->dst_gpr == ntex->src_gpr) {
@@ -1691,20 +1292,20 @@ int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_t
 			}
 		}
 		/* slight hack to make gradients always go into same cf */
-		if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
+		if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
 			bc->force_add_cf = 1;
 	}
 
 	/* cf can contains only alu or only vtx or only tex */
 	if (bc->cf_last == NULL ||
-		bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
+		bc->cf_last->op != CF_OP_TEX ||
 	        bc->force_add_cf) {
 		r = r600_bytecode_add_cf(bc);
 		if (r) {
 			free(ntex);
 			return r;
 		}
-		bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
+		bc->cf_last->op = CF_OP_TEX;
 	}
 	if (ntex->src_gpr >= bc->ngpr) {
 		bc->ngpr = ntex->src_gpr + 1;
@@ -1721,7 +1322,7 @@ int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_t
 	return 0;
 }
 
-int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
+int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
 {
 	int r;
 	r = r600_bytecode_add_cf(bc);
@@ -1729,13 +1330,13 @@ int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
 		return r;
 
 	bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
-	bc->cf_last->inst = inst;
+	bc->cf_last->op = op;
 	return 0;
 }
 
 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
 {
-	return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
+	return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
 }
 
 /* common to all 3 families */
@@ -1770,8 +1371,9 @@ static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecod
 /* common to all 3 families */
 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
 {
-	bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
-			     EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
+	bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(
+					r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
+			    EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
 				S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
 				S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
 				S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
@@ -1801,6 +1403,8 @@ static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecod
 /* r600 only, r700/eg bits in r700_asm.c */
 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
 {
+	unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
+
 	/* don't replace gpr by pv or ps for destination register */
 	bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
 				S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
@@ -1823,7 +1427,7 @@ static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecod
 					S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
 					S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
 					S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
-					S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
+					S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
 					S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
 	} else {
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
@@ -1834,7 +1438,7 @@ static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecod
 					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
 					S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
 					S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
-					S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
+					S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
 					S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
 					S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
 					S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
@@ -1845,7 +1449,7 @@ static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecod
 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
 {
 	*bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
-	*bytecode++ = cf->inst |
+	*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
 			S_SQ_CF_WORD1_BARRIER(1) |
 			S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
 }
@@ -1854,35 +1458,28 @@ static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_byt
 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
 {
 	unsigned id = cf->id;
+	const struct cf_op_info *cfop = r600_isa_cf(cf->op);
+	unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
 
-	switch (cf->inst) {
-	case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-	case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-	case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-	case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+	if (cfop->flags & CF_ALU) {
 		bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
 			S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
 			S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
 			S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
 
-		bc->bytecode[id++] = cf->inst |
+		bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
 			S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
 			S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
 			S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
 					S_SQ_CF_ALU_WORD1_BARRIER(1) |
 					S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
 					S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
-		break;
-	case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-	case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-	case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+	} else if (cfop->flags & CF_FETCH) {
 		if (bc->chip_class == R700)
 			r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
 		else
 			r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
-		break;
-	case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-	case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+	} else if (cfop->flags & CF_EXP) {
 		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
 			S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
 			S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
@@ -1893,44 +1490,25 @@ static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode
 			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
-			cf->output.inst |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
-		break;
-	case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
-	case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
-	case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
-	case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
+	} else if (cfop->flags & CF_STRM) {
 		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
 			S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
 			S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
 			S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
 		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
-			cf->output.inst |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
-		break;
-	case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-	case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-	case V_SQ_CF_WORD1_SQ_CF_INST_POP:
-	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-	case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-	case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+	} else {
 		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
-		bc->bytecode[id++] = cf->inst |
+		bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
 					S_SQ_CF_WORD1_BARRIER(1) |
 			                S_SQ_CF_WORD1_COND(cf->cond) |
 			                S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
-
-		break;
-	default:
-		R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
-		return -EINVAL;
 	}
 	return 0;
 }
@@ -1956,86 +1534,9 @@ int r600_bytecode_build(struct r600_bytecode *bc)
 	/* addr start after all the CF instructions */
 	addr = bc->cf_last->id + 2;
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
-		if (bc->chip_class >= EVERGREEN) {
-			switch (cf->inst) {
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-				/* fetch node need to be 16 bytes aligned*/
-				addr += 3;
-				addr &= 0xFFFFFFFCUL;
-				break;
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
-			case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
-			case CF_NATIVE:
-				break;
-			default:
-				R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
-				return -EINVAL;
-			}
-		} else {
-			switch (cf->inst) {
-			case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-			case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-			case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
-				/* fetch node need to be 16 bytes aligned*/
-				addr += 3;
-				addr &= 0xFFFFFFFCUL;
-				break;
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
-			case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-			case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-			case V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-			case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-			case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
-				break;
-			default:
-				R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
-				return -EINVAL;
-			}
+		if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
+			addr += 3;
+			addr &= 0xFFFFFFFCUL;
 		}
 		cf->addr = addr;
 		addr += cf->ndw;
@@ -2046,185 +1547,68 @@ int r600_bytecode_build(struct r600_bytecode *bc)
 	if (bc->bytecode == NULL)
 		return -ENOMEM;
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
+		const struct cf_op_info *cfop = r600_isa_cf(cf->op);
 		addr = cf->addr;
-		if (bc->chip_class >= EVERGREEN) {
+		if (bc->chip_class >= EVERGREEN)
 			r = eg_bytecode_cf_build(bc, cf);
-			if (r)
-				return r;
-
-			switch (cf->inst) {
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-				nliteral = 0;
-				memset(literal, 0, sizeof(literal));
-				LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
-					r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
-					if (r)
-						return r;
-					r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
-					r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
-
-					switch(bc->chip_class) {
-					case EVERGREEN: /* eg alu is same encoding as r700 */
-					case CAYMAN:
-						r = r700_bytecode_alu_build(bc, alu, addr);
-						break;
-					default:
-						R600_ERR("unknown chip class %d.\n", bc->chip_class);
-						return -EINVAL;
-					}
-					if (r)
-						return r;
-					addr += 2;
-					if (alu->last) {
-						for (i = 0; i < align(nliteral, 2); ++i) {
-							bc->bytecode[addr++] = literal[i];
-						}
-						nliteral = 0;
-						memset(literal, 0, sizeof(literal));
-					}
-				}
-				break;
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-				LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
-					r = r600_bytecode_vtx_build(bc, vtx, addr);
-					if (r)
-						return r;
-					addr += 4;
-				}
-				break;
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-				LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
-					assert(bc->chip_class >= EVERGREEN);
-					r = r600_bytecode_vtx_build(bc, vtx, addr);
-					if (r)
-						return r;
-					addr += 4;
-				}
-				LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
-					r = r600_bytecode_tex_build(bc, tex, addr);
-					if (r)
-						return r;
-					addr += 4;
-				}
-				break;
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
-			case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
-				break;
-			case CF_NATIVE:
-				break;
-			default:
-				R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
-				return -EINVAL;
-			}
-		} else {
+		else
 			r = r600_bytecode_cf_build(bc, cf);
-			if (r)
-				return r;
-
-			switch (cf->inst) {
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-				nliteral = 0;
-				memset(literal, 0, sizeof(literal));
-				LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
-					r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
-					if (r)
-						return r;
-					r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
-					r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
+		if (r)
+			return r;
+		if (cfop->flags & CF_ALU) {
+			nliteral = 0;
+			memset(literal, 0, sizeof(literal));
+			LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
+				r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
+				if (r)
+					return r;
+				r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
+				r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
 
-					switch(bc->chip_class) {
-					case R600:
-						r = r600_bytecode_alu_build(bc, alu, addr);
-						break;
-					case R700:
-						r = r700_bytecode_alu_build(bc, alu, addr);
-						break;
-					default:
-						R600_ERR("unknown chip class %d.\n", bc->chip_class);
-						return -EINVAL;
-					}
-					if (r)
-						return r;
-					addr += 2;
-					if (alu->last) {
-						for (i = 0; i < align(nliteral, 2); ++i) {
-							bc->bytecode[addr++] = literal[i];
-						}
-						nliteral = 0;
-						memset(literal, 0, sizeof(literal));
-					}
-				}
-				break;
-			case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-			case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
-				LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
-					r = r600_bytecode_vtx_build(bc, vtx, addr);
-					if (r)
-						return r;
-					addr += 4;
+				switch(bc->chip_class) {
+				case R600:
+					r = r600_bytecode_alu_build(bc, alu, addr);
+					break;
+				case R700:
+				case EVERGREEN: /* eg alu is same encoding as r700 */
+				case CAYMAN:
+					r = r700_bytecode_alu_build(bc, alu, addr);
+					break;
+				default:
+					R600_ERR("unknown chip class %d.\n", bc->chip_class);
+					return -EINVAL;
 				}
-				break;
-			case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-				LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
-					r = r600_bytecode_tex_build(bc, tex, addr);
-					if (r)
-						return r;
-					addr += 4;
+				if (r)
+					return r;
+				addr += 2;
+				if (alu->last) {
+					for (i = 0; i < align(nliteral, 2); ++i) {
+						bc->bytecode[addr++] = literal[i];
+					}
+					nliteral = 0;
+					memset(literal, 0, sizeof(literal));
 				}
-				break;
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-			case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-			case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-			case V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-			case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
-				break;
-			default:
-				R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
-				return -EINVAL;
+			}
+		} else if (cf->op == CF_OP_VTX) {
+			LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+				r = r600_bytecode_vtx_build(bc, vtx, addr);
+				if (r)
+					return r;
+				addr += 4;
+			}
+		} else if (cf->op == CF_OP_TEX) {
+			LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+				assert(bc->chip_class >= EVERGREEN);
+				r = r600_bytecode_vtx_build(bc, vtx, addr);
+				if (r)
+					return r;
+				addr += 4;
+			}
+			LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
+				r = r600_bytecode_tex_build(bc, tex, addr);
+				if (r)
+					return r;
+				addr += 4;
 			}
 		}
 	}
@@ -2299,13 +1683,12 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
 
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
 		id = cf->id;
-
-		if (bc->chip_class >= EVERGREEN) {
-			switch (cf->inst) {
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-			case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+		if (cf->op == CF_NATIVE) {
+			fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
+			fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
+		} else {
+			const struct cf_op_info *cfop = r600_isa_cf(cf->op);
+			if (cfop->flags & CF_ALU) {
 				if (cf->eg_alu_extended) {
 					fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
 					fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
@@ -2326,192 +1709,61 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
 				fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
 				id++;
 				fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
-				fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
-				fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
-				fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
-				fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
-				fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
-				break;
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-				fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
-				fprintf(stderr, "ADDR:%d\n", cf->addr);
-				id++;
-				fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
-				fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
-				fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
-				break;
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-				fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
-				fprintf(stderr, "GPR:%X ", cf->output.gpr);
-				fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
-				fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
-				fprintf(stderr, "TYPE:%X\n", cf->output.type);
-				id++;
-				fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
-				fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
-				fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
-				fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
-				fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
-				fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
-				fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
-				fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
-				fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
-				break;
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
-			case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
-				fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
-					(EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
-					 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
-					(EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
-					 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
-				fprintf(stderr, "GPR:%X ", cf->output.gpr);
-				fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
-				fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
-				fprintf(stderr, "TYPE:%X\n", cf->output.type);
-				id++;
-				fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
-					(EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
-					 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
-					(EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
-					 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
-				fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
-				fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
-				fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
-				fprintf(stderr, "INST:%d ", cf->output.inst);
-				fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
-				fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
-				break;
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-			case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
-			case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
-				fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
-				fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
-				id++;
-				fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
-				fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
-				fprintf(stderr, "COND:%X ", cf->cond);
-				fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
-				break;
-			case CF_NATIVE:
-				fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
-				fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
-				break;
-			default:
-				R600_ERR("Unknown instruction %0x\n", cf->inst);
-			}
-		} else {
-			switch (cf->inst) {
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
-			case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
-				fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
-				fprintf(stderr, "ADDR:%d ", cf->addr);
-				fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
-				fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
-				fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
-				id++;
-				fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
-				fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
+				fprintf(stderr, "INST: %s ", cfop->name);
 				fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
 				fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
 				fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
 				fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
-				break;
-			case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-			case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-			case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+			} else if (cfop->flags & CF_FETCH) {
 				fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
 				fprintf(stderr, "ADDR:%d\n", cf->addr);
 				id++;
 				fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
-				fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
+				fprintf(stderr, "INST: %s ", cfop->name);
 				fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
-				break;
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
-				fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
+			} else if (cfop->flags & CF_EXP) {
+				fprintf(stderr, "%04d %08X %s ", id, bc->bytecode[id],
+						cfop->name);
 				fprintf(stderr, "GPR:%X ", cf->output.gpr);
 				fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
 				fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
 				fprintf(stderr, "TYPE:%X\n", cf->output.type);
 				id++;
-				fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
+				fprintf(stderr, "%04d %08X %s ", id, bc->bytecode[id],
+						cfop->name);
 				fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
 				fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
 				fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
 				fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
 				fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
-				fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
+				fprintf(stderr, "INST: %s ", r600_isa_cf(cf->op)->name);
 				fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
 				fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
-				break;
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
-			case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
-				fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
-					R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
-					R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
+			} else if (cfop->flags & CF_STRM) {
+				fprintf(stderr, "%04d %08X EXPORT %s ", id, bc->bytecode[id],
+						cfop->name);
 				fprintf(stderr, "GPR:%X ", cf->output.gpr);
 				fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
 				fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
 				fprintf(stderr, "TYPE:%X\n", cf->output.type);
 				id++;
-				fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
-					R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
-					R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
+				fprintf(stderr, "%04d %08X EXPORT %s ", id, bc->bytecode[id],
+				        cfop->name);
 				fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
 				fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
 				fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
-				fprintf(stderr, "INST:%d ", cf->output.inst);
+				fprintf(stderr, "INST: %s ", cfop->name);
 				fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
 				fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
-				break;
-			case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
-			case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
-			case V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
-			case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
-			case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
-			case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+
+			} else {
 				fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
 				fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
 				id++;
 				fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
-				fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
+				fprintf(stderr, "INST: %s ", cfop->name);
 				fprintf(stderr, "COND:%X ", cf->cond);
 				fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
-				break;
-			default:
-				R600_ERR("Unknown instruction %0x\n", cf->inst);
 			}
 		}
 
@@ -2521,7 +1773,7 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
 			r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
 
 			fprintf(stderr, "%04d %08X   ", id, bc->bytecode[id]);
-			fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
+			fprintf(stderr, "  SRC0(SEL:%d ", alu->src[0].sel);
 			fprintf(stderr, "REL:%d ", alu->src[0].rel);
 			fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
 			fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
@@ -2534,7 +1786,7 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
 			fprintf(stderr, "LAST:%d)\n", alu->last);
 			id++;
 			fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
-			fprintf(stderr, "INST:0x%x ", alu->inst);
+			fprintf(stderr, "INST: %s ", r600_isa_alu(alu->op)->name);
 			fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
 			fprintf(stderr, "CHAN:%d ", alu->dst.chan);
 			fprintf(stderr, "REL:%d ", alu->dst.rel);
@@ -2568,7 +1820,7 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
 
 		LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
 			fprintf(stderr, "%04d %08X   ", id, bc->bytecode[id]);
-			fprintf(stderr, "INST:0x%x ", tex->inst);
+			fprintf(stderr, "INST: %s ", r600_isa_fetch(tex->op)->name);
 			fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
 			fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
 			fprintf(stderr, "REL:%d)\n", tex->src_rel);
@@ -2602,7 +1854,7 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
 
 		LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
 			fprintf(stderr, "%04d %08X   ", id, bc->bytecode[id]);
-			fprintf(stderr, "INST:%d ", vtx->inst);
+			fprintf(stderr, "INST: %s ", r600_isa_fetch(vtx->op)->name);
 			fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
 			fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
 			id++;
@@ -2805,13 +2057,15 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
 	r600_bytecode_init(&bc, rctx->chip_class, rctx->family,
 			   rctx->screen->msaa_texture_support);
 
+	bc.isa = rctx->isa;
+
 	for (i = 0; i < count; i++) {
 		if (elements[i].instance_divisor > 1) {
 			if (rctx->chip_class == CAYMAN) {
 				for (j = 0; j < 4; j++) {
 					struct r600_bytecode_alu alu;
 					memset(&alu, 0, sizeof(alu));
-					alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+					alu.op = ALU_OP2_MULHI_UINT;
 					alu.src[0].sel = 0;
 					alu.src[0].chan = 3;
 					alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -2828,7 +2082,7 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
 			} else {
 				struct r600_bytecode_alu alu;
 				memset(&alu, 0, sizeof(alu));
-				alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+				alu.op = ALU_OP2_MULHI_UINT;
 				alu.src[0].sel = 0;
 				alu.src[0].chan = 3;
 				alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -2886,7 +2140,7 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
 		}
 	}
 
-	r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
+	r600_bytecode_add_cfinst(&bc, CF_OP_RET);
 
 	if ((r = r600_bytecode_build(&bc))) {
 		r600_bytecode_clear(&bc);
@@ -2935,7 +2189,8 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
 	return shader;
 }
 
-void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
+void r600_bytecode_alu_read(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
 {
 	/* WORD0 */
 	alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
@@ -2965,13 +2220,16 @@ void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint3
 		alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
 		alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
 		alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
-		alu->inst = G_SQ_ALU_WORD1_OP3_ALU_INST(word1);
+		alu->op = r600_isa_alu_by_opcode(bc->isa,
+				G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
+
 	}
 	else /*ALU_DWORD1_OP2*/
 	{
 		alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
 		alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
-		alu->inst = G_SQ_ALU_WORD1_OP2_ALU_INST(word1);
+		alu->op = r600_isa_alu_by_opcode(bc->isa,
+				G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
 		alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
 		alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
 		alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
@@ -2980,7 +2238,8 @@ void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint3
 	}
 }
 
-void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
+void r600_bytecode_export_read(struct r600_bytecode *bc,
+		struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
 {
 	output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
 	output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
@@ -2993,7 +2252,8 @@ void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t wor
 	output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
 	output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
 	output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
-	output->inst = R600_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
+    output->op = r600_isa_cf_by_opcode(bc->isa,
+			G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
 	output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
 	output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
 	output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 0b33c380098..b3dfc24ff45 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -24,6 +24,7 @@
 #define R600_ASM_H
 
 #include "r600_pipe.h"
+#include "r600_isa.h"
 
 struct r600_bytecode_alu_src {
 	unsigned			sel;
@@ -47,7 +48,7 @@ struct r600_bytecode_alu {
 	struct list_head		list;
 	struct r600_bytecode_alu_src		src[3];
 	struct r600_bytecode_alu_dst		dst;
-	unsigned			inst;
+	unsigned			op;
 	unsigned			last;
 	unsigned			is_op3;
 	unsigned			execute_mask;
@@ -61,7 +62,7 @@ struct r600_bytecode_alu {
 
 struct r600_bytecode_tex {
 	struct list_head		list;
-	unsigned			inst;
+	unsigned			op;
 	unsigned			inst_mod;
 	unsigned			resource_id;
 	unsigned			src_gpr;
@@ -89,7 +90,7 @@ struct r600_bytecode_tex {
 
 struct r600_bytecode_vtx {
 	struct list_head		list;
-	unsigned			inst;
+	unsigned			op;
 	unsigned			fetch_type;
 	unsigned			buffer_id;
 	unsigned			src_gpr;
@@ -116,8 +117,7 @@ struct r600_bytecode_output {
 	unsigned			type;
 	unsigned			end_of_program;
 
-	/* CF_INST. This is already bit-shifted and only needs to be or'd for bytecode. */
-	unsigned			inst;
+	unsigned			op;
 
 	unsigned			elem_size;
 	unsigned			gpr;
@@ -135,20 +135,10 @@ struct r600_bytecode_kcache {
 	unsigned			addr;
 };
 
-/* A value of CF_NATIVE in r600_bytecode_cf::inst means that this instruction
- * has already been encoded, and the encoding has been stored in
- * r600_bytecode::isa.  This is used by the LLVM backend to emit CF instructions
- * e.g. RAT_WRITE_* that can't be properly represented by struct
- * r600_bytecode_cf.
- */
-#define CF_NATIVE ~0
-
 struct r600_bytecode_cf {
 	struct list_head		list;
 
-	/* CF_INST. This is already bit-shifted and only needs to be or'd for bytecode. */
-	unsigned			inst;
-
+	unsigned			op;
 	unsigned			addr;
 	unsigned			ndw;
 	unsigned			id;
@@ -216,6 +206,7 @@ struct r600_bytecode {
 	unsigned	ar_chan;
 	unsigned        ar_handling;
 	unsigned        r6xx_nop_after_rel_dst;
+	struct r600_isa* isa;
 };
 
 /* eg_asm.c */
@@ -227,16 +218,24 @@ void r600_bytecode_init(struct r600_bytecode *bc,
 			enum radeon_family family,
 			enum r600_msaa_texture_mode msaa_texture_mode);
 void r600_bytecode_clear(struct r600_bytecode *bc);
-int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu);
-int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx);
-int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex);
-int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output);
+int r600_bytecode_add_alu(struct r600_bytecode *bc,
+		const struct r600_bytecode_alu *alu);
+int r600_bytecode_add_vtx(struct r600_bytecode *bc,
+		const struct r600_bytecode_vtx *vtx);
+int r600_bytecode_add_tex(struct r600_bytecode *bc,
+		const struct r600_bytecode_tex *tex);
+int r600_bytecode_add_output(struct r600_bytecode *bc,
+		const struct r600_bytecode_output *output);
 int r600_bytecode_build(struct r600_bytecode *bc);
-int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst);
-int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type);
-void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg);
+int r600_bytecode_add_cfinst(struct r600_bytecode *bc,
+		unsigned op);
+int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
+		const struct r600_bytecode_alu *alu, unsigned type);
+void r600_bytecode_special_constants(uint32_t value,
+		unsigned *sel, unsigned *neg);
 void r600_bytecode_dump(struct r600_bytecode *bc);
-void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
+void r600_bytecode_alu_read(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
 
 int cm_bytecode_add_cf_end(struct r600_bytecode *bc);
 
@@ -245,11 +244,16 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
 				      const struct pipe_vertex_element *elements);
 
 /* r700_asm.c */
-void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf);
-int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
-void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
-void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
-void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
+void r700_bytecode_cf_vtx_build(uint32_t *bytecode,
+		const struct r600_bytecode_cf *cf);
+int r700_bytecode_alu_build(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu, unsigned id);
+void r700_bytecode_alu_read(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
+void r600_bytecode_export_read(struct r600_bytecode *bc,
+		struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
+void eg_bytecode_export_read(struct r600_bytecode *bc,
+		struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
 
 void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
 			   unsigned *num_format, unsigned *format_comp, unsigned *endian);
diff --git a/src/gallium/drivers/r600/r600_isa.c b/src/gallium/drivers/r600/r600_isa.c
new file mode 100644
index 00000000000..e3a29c3cdee
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_isa.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2012 Vadim Girlin <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Vadim Girlin
+ */
+
+#include "r600_pipe.h"
+#include "r600_isa.h"
+
+int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa) {
+
+	assert(ctx->chip_class >= R600 && ctx->chip_class <= CAYMAN);
+	isa->hw_class = ctx->chip_class - R600;
+
+	assert(isa->hw_class >= ISA_CC_R600 && isa->hw_class <= ISA_CC_EVERGREEN);
+
+	/* reverse lookup maps are required for bytecode parsing only,
+	 * currently it's needed for handling the bytestream from llvm backend */
+#if defined R600_USE_LLVM || defined HAVE_OPENCL
+	unsigned i, use_llvm;
+
+	use_llvm = debug_get_bool_option("R600_LLVM", TRUE);
+
+	if (!use_llvm)
+		return 0;
+
+	isa->alu_op2_map = calloc(256, sizeof(unsigned));
+	if (!isa->alu_op2_map)
+		return -1;
+	isa->alu_op3_map = calloc(256, sizeof(unsigned));
+	if (!isa->alu_op3_map)
+		return -1;
+	isa->fetch_map = calloc(256, sizeof(unsigned));
+	if (!isa->fetch_map)
+		return -1;
+	isa->cf_map = calloc(256, sizeof(unsigned));
+	if (!isa->cf_map)
+		return -1;
+
+	for (i = 0; i < TABLE_SIZE(alu_op_table); ++i) {
+		const struct alu_op_info *op = &alu_op_table[i];
+		unsigned opc;
+		if (op->flags & AF_LDS || op->slots[isa->hw_class] == 0)
+			continue;
+		opc = op->opcode[isa->hw_class >> 1];
+		assert(opc != -1);
+		if (op->src_count == 3)
+			isa->alu_op3_map[opc] = i + 1;
+		else
+			isa->alu_op2_map[opc] = i + 1;
+	}
+
+	for (i = 0; i < TABLE_SIZE(fetch_op_table); ++i) {
+		const struct fetch_op_info *op = &fetch_op_table[i];
+		unsigned opc = op->opcode[isa->hw_class];
+		if ((op->flags & FF_GDS) || ((opc & 0xFF) != opc))
+			continue; /* ignore GDS ops and INST_MOD versions for now */
+		isa->fetch_map[opc] = i + 1;
+	}
+
+	for (i = 0; i < TABLE_SIZE(cf_op_table); ++i) {
+		const struct cf_op_info *op = &cf_op_table[i];
+		unsigned opc = op->opcode[isa->hw_class];
+		if (opc == -1)
+			continue;
+		/* using offset for CF_ALU_xxx opcodes because they overlap with other
+		 * CF opcodes (they use different encoding in hw) */
+		if (op->flags & CF_ALU)
+			opc += 0x80;
+		isa->cf_map[opc] = i + 1;
+	}
+
+#endif
+	return 0;
+}
+
+int r600_isa_destroy(struct r600_isa *isa) {
+
+	if (!isa)
+		return 0;
+
+	if (isa->alu_op2_map)
+		free(isa->alu_op2_map);
+	if (isa->alu_op3_map)
+		free(isa->alu_op3_map);
+	if (isa->fetch_map)
+		free(isa->fetch_map);
+	if (isa->cf_map)
+		free(isa->cf_map);
+
+	free(isa);
+	return 0;
+}
+
+
+
diff --git a/src/gallium/drivers/r600/r600_isa.h b/src/gallium/drivers/r600/r600_isa.h
new file mode 100644
index 00000000000..5028a951efc
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -0,0 +1,1223 @@
+/*
+ * Copyright 2012 Vadim Girlin <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Vadim Girlin
+ */
+
+#ifndef R600_ISA_H_
+#define R600_ISA_H_
+
+#include "util/u_debug.h"
+
+/* ALU flags */
+enum alu_op_flags
+{
+	AF_V		= (1<<0),    /* allowed in vector slots */
+
+	/* allowed in scalar(trans) slot (slots xyz on cayman, may be replicated
+	 * to w) */
+	AF_S		= (1<<1),
+
+	AF_4SLOT	= (1<<2),            /* uses four vector slots (e.g. DOT4) */
+	AF_4V		= (AF_V | AF_4SLOT),
+	AF_VS		= (AF_V | AF_S),     /* allowed in any slot */
+
+	AF_KILL		= (1<<4),
+	AF_PRED		= (1<<5),
+	AF_SET		= (1<<6),
+
+	/* e.g. MUL_PREV instructions, allowed in x/y, depends on z/w */
+	AF_PREV_INTERLEAVE	= (1<<7),
+
+	AF_MOVA		= (1<<8),    /* all MOVA instructions */
+	AF_IEEE		= (1<<10),
+
+	AF_INT		= (1<<11),   /* integer dst type */
+	AF_UNSIGNED	= (1<<12),   /* unsigned dst (should be used with AF_INT) */
+
+	AF_UINT		= (AF_INT | AF_UNSIGNED),
+
+	/* DP instructions, 2-slot pairs */
+	AF_64		= (1<<13),
+	/* 24 bit instructions */
+	AF_24		= (1<<14),
+	/* DX10 variants */
+	AF_DX10		= (1<<15),
+
+	/* result is replicated to all channels (only if AF_4V is also set -
+	 * for special handling of MULLO_INT on CM) */
+	AF_REPL		= (1<<16),
+
+	/* interpolation instructions */
+	AF_INTERP	= (1<<17),
+
+	/* LDS instructions */
+	AF_LDS		= (1<<20),
+
+	/* e.g. DOT - depends on the next slot in the same group (x<=y/y<=z/z<=w) */
+	AF_PREV_NEXT	= (1<<21),
+
+	/* int<->flt conversions */
+	AF_CVT = (1<<22),
+
+	/* commutative operation on src0 and src1 ( a op b = b op a),
+	 * includes MULADDs (considering the MUL part on src0 and src1 only) */
+	AF_M_COMM = (1 << 23),
+
+	/* associative operation ((a op b) op c) == (a op (b op c))  */
+	AF_M_ASSOC = (1 << 24),
+
+	AF_PRED_PUSH = (1 << 25),
+
+	AF_ANY_PRED = (AF_PRED | AF_PRED_PUSH),
+
+	/* condition codes - 3 bits */
+	AF_CC_SHIFT = 26,
+	AF_CC_MASK	= (7 << AF_CC_SHIFT),
+	AF_CC_E		= (0 << AF_CC_SHIFT),
+	AF_CC_GT	= (1 << AF_CC_SHIFT),
+	AF_CC_GE	= (2 << AF_CC_SHIFT),
+	AF_CC_NE	= (3 << AF_CC_SHIFT),
+	AF_CC_LT	= (4 << AF_CC_SHIFT),
+	AF_CC_LE	= (5 << AF_CC_SHIFT),
+};
+
+/* flags for FETCH instructions (TEX/VTX) */
+enum fetch_op_flags
+{
+	FF_GDS		= (1<<0),
+	FF_TEX		= (1<<1),
+
+	FF_SETGRAD	= (1<<2),
+	FF_USEGRAD	= (1<<3),
+
+	FF_VTX		= (1<<4),
+	FF_MEM		= (1<<5),
+};
+
+/* flags for CF instructions */
+enum cf_op_flags
+{
+	CF_CLAUSE	= (1<<0), 	/* execute clause (alu/fetch ...) */
+	CF_ACK		= (1<<1),	/* acked versions of some instructions */
+	CF_ALU		= (1<<2),	/* alu clause execution */
+	CF_ALU_EXT	= (1<<3),	/* ALU_EXTENDED */
+	CF_EXP		= (1<<4),	/* export (CF_ALLOC_EXPORT_WORD1_SWIZ) */
+	CF_BRANCH	= (1<<5),   /* branch instructions */
+	CF_LOOP		= (1<<6),   /* loop instructions */
+	CF_CALL		= (1<<7),   /* call instructions */
+	CF_MEM		= (1<<8),	/* export_mem (CF_ALLOC_EXPORT_WORD1_BUF) */
+	CF_FETCH	= (1<<9),	/* fetch clause */
+
+	CF_UNCOND	= (1<<10),	/* COND = ACTIVE required */
+	CF_EMIT		= (1<<11),
+	CF_STRM		= (1<<12),	/* MEM_STREAM* */
+
+	CF_LOOP_START = (1<<13)
+};
+
+/* ALU instruction info */
+struct alu_op_info
+{
+	/* instruction name */
+	const char	*name;
+	/* number of source operands */
+	int	src_count;
+	/* opcodes, [0] - for r6xx/r7xx, [1] - for evergreen/cayman
+	 * (-1) if instruction doesn't exist (more precise info in "slots") */
+	int opcode[2];
+	/* slots for r6xx, r7xx, evergreen, cayman
+	 * (0 if instruction doesn't exist for chip class) */
+	int	slots[4];
+	/* flags (mostly autogenerated from instruction name) */
+	int	flags;
+};
+
+/* FETCH instruction info */
+struct fetch_op_info
+{
+	const char * name;
+	/* for every chip class */
+	int opcode[4];
+	int flags;
+};
+
+/* CF instruction info */
+struct cf_op_info
+{
+	const char * name;
+	/* for every chip class */
+	int opcode[4];
+	int flags;
+};
+
+static const struct alu_op_info alu_op_table[] = {
+		{"ADD",                       2, { 0x00, 0x00 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
+		{"MUL",                       2, { 0x01, 0x01 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
+		{"MUL_IEEE",                  2, { 0x02, 0x02 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_IEEE },
+		{"MAX",                       2, { 0x03, 0x03 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
+		{"MIN",                       2, { 0x04, 0x04 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
+		{"MAX_DX10",                  2, { 0x05, 0x05 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_DX10 },
+		{"MIN_DX10",                  2, { 0x06, 0x06 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_DX10 },
+		{"SETE",                      2, { 0x08, 0x08 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_E },
+		{"SETGT",                     2, { 0x09, 0x09 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT },
+		{"SETGE",                     2, { 0x0A, 0x0A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE },
+		{"SETNE",                     2, { 0x0B, 0x0B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_NE },
+		{"SETE_DX10",                 2, { 0x0C, 0x0C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_E | AF_DX10 },
+		{"SETGT_DX10",                2, { 0x0D, 0x0D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT | AF_DX10 },
+		{"SETGE_DX10",                2, { 0x0E, 0x0E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE | AF_DX10 },
+		{"SETNE_DX10",                2, { 0x0F, 0x0F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_NE | AF_DX10 },
+		{"FRACT",                     1, { 0x10, 0x10 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"TRUNC",                     1, { 0x11, 0x11 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"CEIL",                      1, { 0x12, 0x12 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"RNDNE",                     1, { 0x13, 0x13 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"FLOOR",                     1, { 0x14, 0x14 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"ASHR_INT",                  2, { 0x70, 0x15 },{   AF_S, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"LSHR_INT",                  2, { 0x71, 0x16 },{   AF_S, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"LSHL_INT",                  2, { 0x72, 0x17 },{   AF_S, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"MOV",                       1, { 0x19, 0x19 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"ALU_NOP",                   0, { 0x1A, 0x1A },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"PRED_SETGT_UINT",           2, { 0x1E, 0x1E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GT | AF_UINT },
+		{"PRED_SETGE_UINT",           2, { 0x1F, 0x1F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GE | AF_UINT },
+		{"PRED_SETE",                 2, { 0x20, 0x20 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_E },
+		{"PRED_SETGT",                2, { 0x21, 0x21 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GT },
+		{"PRED_SETGE",                2, { 0x22, 0x22 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GE },
+		{"PRED_SETNE",                2, { 0x23, 0x23 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_NE },
+		{"PRED_SET_INV",              1, { 0x24, 0x24 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
+		{"PRED_SET_POP",              2, { 0x25, 0x25 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
+		{"PRED_SET_CLR",              0, { 0x26, 0x26 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
+		{"PRED_SET_RESTORE",          1, { 0x27, 0x27 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
+		{"PRED_SETE_PUSH",            2, { 0x28, 0x28 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_E },
+		{"PRED_SETGT_PUSH",           2, { 0x29, 0x29 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GT },
+		{"PRED_SETGE_PUSH",           2, { 0x2A, 0x2A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GE },
+		{"PRED_SETNE_PUSH",           2, { 0x2B, 0x2B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_NE },
+		{"KILLE",                     2, { 0x2C, 0x2C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_E },
+		{"KILLGT",                    2, { 0x2D, 0x2D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GT },
+		{"KILLGE",                    2, { 0x2E, 0x2E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GE },
+		{"KILLNE",                    2, { 0x2F, 0x2F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_NE },
+		{"AND_INT",                   2, { 0x30, 0x30 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT },
+		{"OR_INT",                    2, { 0x31, 0x31 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT },
+		{"XOR_INT",                   2, { 0x32, 0x32 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT },
+		{"NOT_INT",                   1, { 0x33, 0x33 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"ADD_INT",                   2, { 0x34, 0x34 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT },
+		{"SUB_INT",                   2, { 0x35, 0x35 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"MAX_INT",                   2, { 0x36, 0x36 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT },
+		{"MIN_INT",                   2, { 0x37, 0x37 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT },
+		{"MAX_UINT",                  2, { 0x38, 0x38 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_UINT },
+		{"MIN_UINT",                  2, { 0x39, 0x39 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_UINT },
+		{"SETE_INT",                  2, { 0x3A, 0x3A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_E | AF_INT },
+		{"SETGT_INT",                 2, { 0x3B, 0x3B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT | AF_INT },
+		{"SETGE_INT",                 2, { 0x3C, 0x3C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE | AF_INT },
+		{"SETNE_INT",                 2, { 0x3D, 0x3D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_NE | AF_INT },
+		{"SETGT_UINT",                2, { 0x3E, 0x3E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT | AF_UINT },
+		{"SETGE_UINT",                2, { 0x3F, 0x3F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE | AF_UINT },
+		{"KILLGT_UINT",               2, { 0x40, 0x40 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GT | AF_UINT },
+		{"KILLGE_UINT",               2, { 0x41, 0x41 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GE | AF_UINT },
+		{"PRED_SETE_INT",             2, { 0x42, 0x42 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_E | AF_INT },
+		{"PRED_SETGT_INT",            2, { 0x43, 0x43 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GT | AF_INT },
+		{"PRED_SETGE_INT",            2, { 0x44, 0x44 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GE | AF_INT },
+		{"PRED_SETNE_INT",            2, { 0x45, 0x45 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_NE | AF_INT },
+		{"KILLE_INT",                 2, { 0x46, 0x46 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_E | AF_INT },
+		{"KILLGT_INT",                2, { 0x47, 0x47 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GT | AF_INT },
+		{"KILLGE_INT",                2, { 0x48, 0x48 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GE | AF_INT },
+		{"KILLNE_INT",                2, { 0x49, 0x49 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_NE | AF_INT },
+		{"PRED_SETE_PUSH_INT",        2, { 0x4A, 0x4A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_E | AF_INT },
+		{"PRED_SETGT_PUSH_INT",       2, { 0x4B, 0x4B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GT | AF_INT },
+		{"PRED_SETGE_PUSH_INT",       2, { 0x4C, 0x4C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GE | AF_INT },
+		{"PRED_SETNE_PUSH_INT",       2, { 0x4D, 0x4D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_NE | AF_INT },
+		{"PRED_SETLT_PUSH_INT",       2, { 0x4E, 0x4E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_LT | AF_INT },
+		{"PRED_SETLE_PUSH_INT",       2, { 0x4F, 0x4F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_LE | AF_INT },
+		{"FLT_TO_INT",                1, { 0x6B, 0x50 },{   AF_S,  AF_S, AF_VS, AF_VS},  AF_INT | AF_CVT },
+		{"BFREV_INT",                 1, {   -1, 0x51 },{      0,     0, AF_VS, AF_VS},  AF_INT },
+		{"ADDC_UINT",                 2, {   -1, 0x52 },{      0,     0, AF_VS, AF_VS},  AF_UINT },
+		{"SUBB_UINT",                 2, {   -1, 0x53 },{      0,     0, AF_VS, AF_VS},  AF_UINT },
+		{"GROUP_BARRIER",             0, {   -1, 0x54 },{      0,     0, AF_VS, AF_VS},  0 },
+		{"GROUP_SEQ_BEGIN",           0, {   -1, 0x55 },{      0,     0, AF_VS,     0},  0 },
+		{"GROUP_SEQ_END",             0, {   -1, 0x56 },{      0,     0, AF_VS,     0},  0 },
+		{"SET_MODE",                  2, {   -1, 0x57 },{      0,     0, AF_VS, AF_VS},  0 },
+		{"SET_CF_IDX0",               0, {   -1, 0x58 },{      0,     0, AF_VS,     0},  0 },
+		{"SET_CF_IDX1",               0, {   -1, 0x59 },{      0,     0, AF_VS,     0},  0 },
+		{"SET_LDS_SIZE",              2, {   -1, 0x5A },{      0,     0, AF_VS, AF_VS},  0 },
+		{"MUL_INT24",                 2, {   -1, 0x5B },{      0,     0,     0,  AF_V},  AF_INT | AF_24 },
+		{"MULHI_INT24",               2, {   -1, 0x5C },{      0,     0,     0,  AF_V},  AF_INT | AF_24 },
+		{"FLT_TO_INT_TRUNC",          1, {   -1, 0x5D },{      0,     0,     0,  AF_V},  AF_INT | AF_CVT},
+		{"EXP_IEEE",                  1, { 0x61, 0x81 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
+		{"LOG_CLAMPED",               1, { 0x62, 0x82 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"LOG_IEEE",                  1, { 0x63, 0x83 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
+		{"RECIP_CLAMPED",             1, { 0x64, 0x84 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"RECIP_FF",                  1, { 0x65, 0x85 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"RECIP_IEEE",                1, { 0x66, 0x86 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
+		{"RECIPSQRT_CLAMPED",         1, { 0x67, 0x87 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"RECIPSQRT_FF",              1, { 0x68, 0x88 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"RECIPSQRT_IEEE",            1, { 0x69, 0x89 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
+		{"SQRT_IEEE",                 1, { 0x6A, 0x8A },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
+		{"SIN",                       1, { 0x6E, 0x8D },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"COS",                       1, { 0x6F, 0x8E },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
+		{"MULLO_INT",                 2, { 0x73, 0x8F },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_INT | AF_REPL},
+		{"MULHI_INT",                 2, { 0x74, 0x90 },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_INT | AF_REPL},
+		{"MULLO_UINT",                2, { 0x75, 0x91 },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_UINT | AF_REPL},
+		{"MULHI_UINT",                2, { 0x76, 0x92 },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_UINT | AF_REPL},
+		{"RECIP_INT",                 1, { 0x77, 0x93 },{   AF_S,  AF_S,  AF_S,     0},  AF_INT },
+		{"RECIP_UINT",                1, { 0x78, 0x94 },{   AF_S,  AF_S,  AF_S,     0},  AF_UINT },
+		{"RECIP_64",                  2, {   -1, 0x95 },{      0,     0,  AF_S,  AF_S},  AF_64 },
+		{"RECIP_CLAMPED_64",          2, {   -1, 0x96 },{      0,     0,  AF_S,  AF_S},  AF_64 },
+		{"RECIPSQRT_64",              2, {   -1, 0x97 },{      0,     0,  AF_S,  AF_S},  AF_64 },
+		{"RECIPSQRT_CLAMPED_64",      2, {   -1, 0x98 },{      0,     0,  AF_S,  AF_S},  AF_64 },
+		{"SQRT_64",                   2, {   -1, 0x99 },{      0,     0,  AF_S,  AF_S},  AF_64 },
+		{"FLT_TO_UINT",               1, { 0x79, 0x9A },{   AF_S,  AF_S,  AF_S,  AF_V},  AF_UINT | AF_CVT},
+		{"INT_TO_FLT",                1, { 0x6C, 0x9B },{   AF_S,  AF_S,  AF_S,  AF_V},  AF_CVT},
+		{"UINT_TO_FLT",               1, { 0x6D, 0x9C },{   AF_S,  AF_S,  AF_S,  AF_V},  AF_CVT },
+		{"BFM_INT",                   2, {   -1, 0xA0 },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"FLT32_TO_FLT16",            1, {   -1, 0xA2 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"FLT16_TO_FLT32",            1, {   -1, 0xA3 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"UBYTE0_FLT",                1, {   -1, 0xA4 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"UBYTE1_FLT",                1, {   -1, 0xA5 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"UBYTE2_FLT",                1, {   -1, 0xA6 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"UBYTE3_FLT",                1, {   -1, 0xA7 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"BCNT_INT",                  1, {   -1, 0xAA },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"FFBH_UINT",                 1, {   -1, 0xAB },{      0,     0,  AF_V,  AF_V},  AF_UINT },
+		{"FFBL_INT",                  1, {   -1, 0xAC },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"FFBH_INT",                  1, {   -1, 0xAD },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"FLT_TO_UINT4",              1, {   -1, 0xAE },{      0,     0,  AF_V,  AF_V},  AF_UINT },
+		{"DOT_IEEE",                  2, {   -1, 0xAF },{      0,     0,  AF_V,  AF_V},  AF_PREV_NEXT | AF_IEEE },
+		{"FLT_TO_INT_RPI",            1, {   -1, 0xB0 },{      0,     0,  AF_V,  AF_V},  AF_INT | AF_CVT},
+		{"FLT_TO_INT_FLOOR",          1, {   -1, 0xB1 },{      0,     0,  AF_V,  AF_V},  AF_INT | AF_CVT},
+		{"MULHI_UINT24",              2, {   -1, 0xB2 },{      0,     0,  AF_V,  AF_V},  AF_UINT | AF_24 },
+		{"MBCNT_32HI_INT",            1, {   -1, 0xB3 },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"OFFSET_TO_FLT",             1, {   -1, 0xB4 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"MUL_UINT24",                2, {   -1, 0xB5 },{      0,     0,  AF_V,  AF_V},  AF_UINT | AF_24 },
+		{"BCNT_ACCUM_PREV_INT",       1, {   -1, 0xB6 },{      0,     0,  AF_V,  AF_V},  AF_INT | AF_PREV_NEXT },
+		{"MBCNT_32LO_ACCUM_PREV_INT", 1, {   -1, 0xB7 },{      0,     0,  AF_V,  AF_V},  AF_INT | AF_PREV_NEXT },
+		{"SETE_64",                   2, {   -1, 0xB8 },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_E | AF_64 },
+		{"SETNE_64",                  2, {   -1, 0xB9 },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_NE | AF_64 },
+		{"SETGT_64",                  2, {   -1, 0xBA },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_GT | AF_64 },
+		{"SETGE_64",                  2, {   -1, 0xBB },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_GE | AF_64 },
+		{"MIN_64",                    2, {   -1, 0xBC },{      0,     0,  AF_V,  AF_V},  AF_64 },
+		{"MAX_64",                    2, {   -1, 0xBD },{      0,     0,  AF_V,  AF_V},  AF_64 },
+		{"DOT4",                      2, { 0x50, 0xBE },{  AF_4V, AF_4V, AF_4V, AF_4V},  AF_REPL },
+		{"DOT4_IEEE",                 2, { 0x51, 0xBF },{  AF_4V, AF_4V, AF_4V, AF_4V},  AF_REPL | AF_IEEE  },
+		{"CUBE",                      2, { 0x52, 0xC0 },{  AF_4V, AF_4V, AF_4V, AF_4V},  0 },
+		{"MAX4",                      1, { 0x53, 0xC1 },{  AF_4V, AF_4V, AF_4V, AF_4V},  AF_REPL },
+		{"FREXP_64",                  1, { 0x07, 0xC4 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
+		{"LDEXP_64",                  2, { 0x7A, 0xC5 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
+		{"FRACT_64",                  1, { 0x7B, 0xC6 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
+		{"PRED_SETGT_64",             2, { 0x7C, 0xC7 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_PRED | AF_CC_GT | AF_64 },
+		{"PRED_SETE_64",              2, { 0x7D, 0xC8 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_PRED | AF_CC_E | AF_64 },
+		{"PRED_SETGE_64",             2, { 0x7E, 0xC9 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_PRED | AF_CC_GE | AF_64 },
+		{"MUL_64",                    2, { 0x1B, 0xCA },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
+		{"ADD_64",                    2, { 0x17, 0xCB },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
+		{"MOVA_INT",                  1, { 0x18, 0xCC },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_MOVA | AF_INT },
+		{"FLT64_TO_FLT32",            1, { 0x1C, 0xCD },{   AF_V,  AF_V,  AF_V,  AF_V},  0 },
+		{"FLT32_TO_FLT64",            1, { 0x1D, 0xCE },{   AF_V,  AF_V,  AF_V,  AF_V},  0 },
+		{"SAD_ACCUM_PREV_UINT",       2, {   -1, 0xCF },{      0,     0,  AF_V,  AF_V},  AF_UINT | AF_PREV_NEXT },
+		{"DOT",                       2, {   -1, 0xD0 },{      0,     0,  AF_V,  AF_V},  AF_PREV_NEXT },
+		{"MUL_PREV",                  1, {   -1, 0xD1 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE },
+		{"MUL_IEEE_PREV",             1, {   -1, 0xD2 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE | AF_IEEE },
+		{"ADD_PREV",                  1, {   -1, 0xD3 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE },
+		{"MULADD_PREV",               2, {   -1, 0xD4 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE },
+		{"MULADD_IEEE_PREV",          2, {   -1, 0xD5 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE | AF_IEEE },
+		{"INTERP_XY",                 2, {   -1, 0xD6 },{      0,     0, AF_4V, AF_4V},  AF_INTERP },
+		{"INTERP_ZW",                 2, {   -1, 0xD7 },{      0,     0, AF_4V, AF_4V},  AF_INTERP },
+		{"INTERP_X",                  2, {   -1, 0xD8 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
+		{"INTERP_Z",                  2, {   -1, 0xD9 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
+		{"STORE_FLAGS",               1, {   -1, 0xDA },{      0,     0,  AF_V,  AF_V},  0 },
+		{"LOAD_STORE_FLAGS",          1, {   -1, 0xDB },{      0,     0,  AF_V,  AF_V},  0 },
+		{"LDS_1A",                    2, {   -1, 0xDC },{      0,     0,  AF_V,  AF_V},  0 },
+		{"LDS_1A1D",                  2, {   -1, 0xDD },{      0,     0,  AF_V,  AF_V},  0 },
+		{"LDS_2A",                    2, {   -1, 0xDF },{      0,     0,  AF_V,  AF_V},  0 },
+		{"INTERP_LOAD_P0",            1, {   -1, 0xE0 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"INTERP_LOAD_P10",           1, {   -1, 0xE1 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"INTERP_LOAD_P20",           1, {   -1, 0xE2 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"BFE_UINT",                  3, {   -1, 0x04 },{      0,     0,  AF_V,  AF_V},  AF_UINT },
+		{"BFE_INT",                   3, {   -1, 0x05 },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"BFI_INT",                   3, {   -1, 0x06 },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"FMA",                       3, {   -1, 0x07 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"MULADD_INT24",              3, {   -1, 0x08 },{      0,     0,     0,  AF_V},  AF_INT | AF_24 },
+		{"CNDNE_64",                  3, {   -1, 0x09 },{      0,     0,  AF_V,  AF_V},  AF_64 },
+		{"FMA_64",                    3, {   -1, 0x0A },{      0,     0,  AF_V,  AF_V},  AF_64 },
+		{"LERP_UINT",                 3, {   -1, 0x0B },{      0,     0,  AF_V,  AF_V},  AF_UINT },
+		{"BIT_ALIGN_INT",             3, {   -1, 0x0C },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"BYTE_ALIGN_INT",            3, {   -1, 0x0D },{      0,     0,  AF_V,  AF_V},  AF_INT },
+		{"SAD_ACCUM_UINT",            3, {   -1, 0x0E },{      0,     0,  AF_V,  AF_V},  AF_UINT },
+		{"SAD_ACCUM_HI_UINT",         3, {   -1, 0x0F },{      0,     0,  AF_V,  AF_V},  AF_UINT },
+		{"MULADD_UINT24",             3, {   -1, 0x10 },{      0,     0,  AF_V,  AF_V},  AF_UINT | AF_24 },
+		{"LDS_IDX_OP",                3, {   -1, 0x11 },{      0,     0,  AF_V,  AF_V},  0 },
+		{"MULADD",                    3, { 0x10, 0x14 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM },
+		{"MULADD_M2",                 3, { 0x11, 0x15 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM },
+		{"MULADD_M4",                 3, { 0x12, 0x16 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM },
+		{"MULADD_D2",                 3, { 0x13, 0x17 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM },
+		{"MULADD_IEEE",               3, { 0x14, 0x18 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_IEEE },
+		{"CNDE",                      3, { 0x18, 0x19 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"CNDGT",                     3, { 0x19, 0x1A },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"CNDGE",                     3, { 0x1A, 0x1B },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
+		{"CNDE_INT",                  3, { 0x1C, 0x1C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"CNDGT_INT",                 3, { 0x1D, 0x1D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"CNDGE_INT",                 3, { 0x1E, 0x1E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT },
+		{"MUL_LIT",                   3, { 0x0C, 0x1F },{   AF_S,  AF_S,  AF_S,  AF_V},  0 },
+
+		{"MOVA",                      1, { 0x15,   -1 },{   AF_V,  AF_V,     0,     0},  AF_MOVA },
+		{"MOVA_FLOOR",                1, { 0x16,   -1 },{   AF_V,  AF_V,     0,     0},  AF_MOVA },
+		{"MOVA_GPR_INT",              1, { 0x60,   -1 },{   AF_S,     0,     0,     0},  AF_MOVA | AF_INT },
+
+		{"MULADD_64",                 3, { 0x08,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
+		{"MULADD_64_M2",              3, { 0x09,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
+		{"MULADD_64_M4",              3, { 0x0A,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
+		{"MULADD_64_D2",              3, { 0x0B,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
+		{"MUL_LIT_M2",                3, { 0x0D,   -1 },{  AF_VS, AF_VS,     0,     0},  0 },
+		{"MUL_LIT_M4",                3, { 0x0E,   -1 },{  AF_VS, AF_VS,     0,     0},  0 },
+		{"MUL_LIT_D2",                3, { 0x0F,   -1 },{  AF_VS, AF_VS,     0,     0},  0 },
+		{"MULADD_IEEE_M2",            3, { 0x15,   -1 },{  AF_VS, AF_VS,     0,     0},  AF_IEEE },
+		{"MULADD_IEEE_M4",            3, { 0x16,   -1 },{  AF_VS, AF_VS,     0,     0},  AF_IEEE },
+		{"MULADD_IEEE_D2",            3, { 0x17,   -1 },{  AF_VS, AF_VS,     0,     0},  AF_IEEE },
+
+		{"LDS_ADD",                   2, {   -1, 0x0011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_SUB",                   2, {   -1, 0x0111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_RSUB",                  2, {   -1, 0x0211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_INC",                   2, {   -1, 0x0311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_DEC",                   2, {   -1, 0x0411 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_MIN_INT",               2, {   -1, 0x0511 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT },
+		{"LDS_MAX_INT",               2, {   -1, 0x0611 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT },
+		{"LDS_MIN_UINT",              2, {   -1, 0x0711 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT },
+		{"LDS_MAX_UINT",              2, {   -1, 0x0811 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT },
+		{"LDS_AND",                   2, {   -1, 0x0911 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_OR",                    2, {   -1, 0x0A11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_XOR",                   2, {   -1, 0x0B11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_MSKOR",                 3, {   -1, 0x0C11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_WRITE",                 2, {   -1, 0x0D11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_WRITE_REL",             3, {   -1, 0x0E11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_WRITE2",                3, {   -1, 0x0F11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_CMP_STORE",             3, {   -1, 0x1011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_CMP_STORE_SPF",         3, {   -1, 0x1111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_BYTE_WRITE",            2, {   -1, 0x1211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_SHORT_WRITE",           2, {   -1, 0x1311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_ADD_RET",               2, {   -1, 0x2011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_SUB_RET",               2, {   -1, 0x2111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_RSUB_RET",              2, {   -1, 0x2211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_INC_RET",               2, {   -1, 0x2311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_DEC_RET",               2, {   -1, 0x2411 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_MIN_INT_RET",           2, {   -1, 0x2511 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT },
+		{"LDS_MAX_INT_RET",           2, {   -1, 0x2611 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT },
+		{"LDS_MIN_UINT_RET",          2, {   -1, 0x2711 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT },
+		{"LDS_MAX_UINT_RET",          2, {   -1, 0x2811 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT },
+		{"LDS_AND_RET",               2, {   -1, 0x2911 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_OR_RET",                2, {   -1, 0x2A11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_XOR_RET",               2, {   -1, 0x2B11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_MSKOR_RET",             3, {   -1, 0x2C11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_XCHG_RET",              2, {   -1, 0x2D11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_XCHG_REL_RET",          3, {   -1, 0x2E11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_XCHG2_RET",             3, {   -1, 0x2F11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_CMP_XCHG_RET",          3, {   -1, 0x3011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_CMP_XCHG_SPF_RET",      3, {   -1, 0x3111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_READ_RET",              1, {   -1, 0x3211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_READ_REL_RET",          1, {   -1, 0x3311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_READ2_RET",             2, {   -1, 0x3411 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_READWRITE_RET",         3, {   -1, 0x3511 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_BYTE_READ_RET",         1, {   -1, 0x3611 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_UBYTE_READ_RET",        1, {   -1, 0x3711 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_SHORT_READ_RET",        1, {   -1, 0x3811 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+		{"LDS_USHORT_READ_RET",       1, {   -1, 0x3911 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
+};
+
+static const struct fetch_op_info fetch_op_table[] = {
+		{"VFETCH",                        { 0x000000,  0x000000,  0x000000,  0x000000 }, FF_VTX },
+		{"SEMFETCH",                      { 0x000001,  0x000001,  0x000001,  0x000001 }, FF_VTX },
+
+		{"READ_SCRATCH",                  {       -1,  0x000002,  0x000002,  0x000002 }, FF_VTX | FF_MEM },
+		{"READ_REDUCT",                   {       -1,  0x000102,        -1,        -1 }, FF_VTX | FF_MEM },
+		{"READ_MEM",                      {       -1,  0x000202,  0x000202,  0x000202 }, FF_VTX | FF_MEM },
+		{"DS_LOCAL_WRITE",                {       -1,  0x000402,        -1,        -1 }, FF_VTX | FF_MEM },
+		{"DS_LOCAL_READ",                 {       -1,  0x000502,        -1,        -1 }, FF_VTX | FF_MEM },
+
+		{"GDS_ADD",                       {       -1,        -1,  0x020002,  0x020002 }, FF_GDS },
+		{"GDS_SUB",                       {       -1,        -1,  0x020102,  0x020102 }, FF_GDS },
+		{"GDS_RSUB",                      {       -1,        -1,  0x020202,  0x020202 }, FF_GDS },
+		{"GDS_INC",                       {       -1,        -1,  0x020302,  0x020302 }, FF_GDS },
+		{"GDS_DEC",                       {       -1,        -1,  0x020402,  0x020402 }, FF_GDS },
+		{"GDS_MIN_INT",                   {       -1,        -1,  0x020502,  0x020502 }, FF_GDS },
+		{"GDS_MAX_INT",                   {       -1,        -1,  0x020602,  0x020602 }, FF_GDS },
+		{"GDS_MIN_UINT",                  {       -1,        -1,  0x020702,  0x020702 }, FF_GDS },
+		{"GDS_MAX_UINT",                  {       -1,        -1,  0x020802,  0x020802 }, FF_GDS },
+		{"GDS_AND",                       {       -1,        -1,  0x020902,  0x020902 }, FF_GDS },
+		{"GDS_OR",                        {       -1,        -1,  0x020A02,  0x020A02 }, FF_GDS },
+		{"GDS_XOR",                       {       -1,        -1,  0x020B02,  0x020B02 }, FF_GDS },
+		{"GDS_MSKOR",                     {       -1,        -1,  0x030C02,  0x030C02 }, FF_GDS },
+		{"GDS_WRITE",                     {       -1,        -1,  0x020D02,  0x020D02 }, FF_GDS },
+		{"GDS_WRITE_REL",                 {       -1,        -1,  0x030E02,  0x030E02 }, FF_GDS },
+		{"GDS_WRITE2",                    {       -1,        -1,  0x030F02,  0x030F02 }, FF_GDS },
+		{"GDS_CMP_STORE",                 {       -1,        -1,  0x031002,  0x031002 }, FF_GDS },
+		{"GDS_CMP_STORE_SPF",             {       -1,        -1,  0x031102,  0x031102 }, FF_GDS },
+		{"GDS_BYTE_WRITE",                {       -1,        -1,  0x021202,  0x021202 }, FF_GDS },
+		{"GDS_SHORT_WRITE",               {       -1,        -1,  0x021302,  0x021302 }, FF_GDS },
+		{"GDS_ADD_RET",                   {       -1,        -1,  0x122002,  0x122002 }, FF_GDS },
+		{"GDS_SUB_RET",                   {       -1,        -1,  0x122102,  0x122102 }, FF_GDS },
+		{"GDS_RSUB_RET",                  {       -1,        -1,  0x122202,  0x122202 }, FF_GDS },
+		{"GDS_INC_RET",                   {       -1,        -1,  0x122302,  0x122302 }, FF_GDS },
+		{"GDS_DEC_RET",                   {       -1,        -1,  0x122402,  0x122402 }, FF_GDS },
+		{"GDS_MIN_INT_RET",               {       -1,        -1,  0x122502,  0x122502 }, FF_GDS },
+		{"GDS_MAX_INT_RET",               {       -1,        -1,  0x122602,  0x122602 }, FF_GDS },
+		{"GDS_MIN_UINT_RET",              {       -1,        -1,  0x122702,  0x122702 }, FF_GDS },
+		{"GDS_MAX_UINT_RET",              {       -1,        -1,  0x122802,  0x122802 }, FF_GDS },
+		{"GDS_AND_RET",                   {       -1,        -1,  0x122902,  0x122902 }, FF_GDS },
+		{"GDS_OR_RET",                    {       -1,        -1,  0x122A02,  0x122A02 }, FF_GDS },
+		{"GDS_XOR_RET",                   {       -1,        -1,  0x122B02,  0x122B02 }, FF_GDS },
+		{"GDS_MSKOR_RET",                 {       -1,        -1,  0x132C02,  0x132C02 }, FF_GDS },
+		{"GDS_XCHG_RET",                  {       -1,        -1,  0x122D02,  0x122D02 }, FF_GDS },
+		{"GDS_XCHG_REL_RET",              {       -1,        -1,  0x232E02,  0x232E02 }, FF_GDS },
+		{"GDS_XCHG2_RET",                 {       -1,        -1,  0x232F02,  0x232F02 }, FF_GDS },
+		{"GDS_CMP_XCHG_RET",              {       -1,        -1,  0x133002,  0x133002 }, FF_GDS },
+		{"GDS_CMP_XCHG_SPF_RET",          {       -1,        -1,  0x133102,  0x133102 }, FF_GDS },
+		{"GDS_READ_RET",                  {       -1,        -1,  0x113202,  0x113202 }, FF_GDS },
+		{"GDS_READ_REL_RET",              {       -1,        -1,  0x213302,  0x213302 }, FF_GDS },
+		{"GDS_READ2_RET",                 {       -1,        -1,  0x223402,  0x223402 }, FF_GDS },
+		{"GDS_READWRITE_RET",             {       -1,        -1,  0x133502,  0x133502 }, FF_GDS },
+		{"GDS_BYTE_READ_RET",             {       -1,        -1,  0x113602,  0x113602 }, FF_GDS },
+		{"GDS_UBYTE_READ_RET",            {       -1,        -1,  0x113702,  0x113702 }, FF_GDS },
+		{"GDS_SHORT_READ_RET",            {       -1,        -1,  0x113802,  0x113802 }, FF_GDS },
+		{"GDS_USHORT_READ_RET",           {       -1,        -1,  0x113902,  0x113902 }, FF_GDS },
+		{"GDS_ATOMIC_ORDERED_ALLOC",      {       -1,        -1,  0x113F02,  0x113F02 }, FF_GDS },
+
+		{"TF_WRITE",                      {       -1,        -1,  0x020502,  0x020502 }, FF_GDS },
+
+		{"DS_GLOBAL_WRITE",               {       -1,  0x000602,        -1,        -1 }, 0 },
+		{"DS_GLOBAL_READ",                {       -1,  0x000702,        -1,        -1 }, 0 },
+
+		{"LD",                            { 0x000003,  0x000003,  0x000003,  0x000003 }, 0 },
+		{"LDFPTR",                        {       -1,        -1,  0x000103,  0x000103 }, 0 },
+		{"GET_TEXTURE_RESINFO",           { 0x000004,  0x000004,  0x000004,  0x000004 }, 0 },
+		{"GET_NUMBER_OF_SAMPLES",         { 0x000005,  0x000005,  0x000005,  0x000005 }, 0 },
+		{"GET_LOD",                       { 0x000006,  0x000006,  0x000006,  0x000006 }, 0 },
+		{"GET_GRADIENTS_H",               { 0x000007,  0x000007,  0x000007,  0x000007 }, 0 },
+		{"GET_GRADIENTS_V",               { 0x000008,  0x000008,  0x000008,  0x000008 }, 0 },
+		{"GET_GRADIENTS_H_FINE",          {       -1,        -1,  0x000107,  0x000107 }, 0 },
+		{"GET_GRADIENTS_V_FINE",          {       -1,        -1,  0x000108,  0x000108 }, 0 },
+		{"GET_LERP",                      { 0x000009,  0x000009,        -1,        -1 }, 0 },
+		{"SET_TEXTURE_OFFSETS",           {       -1,        -1,  0x000009,  0x000009 }, 0 },
+		{"KEEP_GRADIENTS",                {       -1,  0x00000A,  0x00000A,  0x00000A }, 0 },
+		{"SET_GRADIENTS_H",               { 0x00000B,  0x00000B,  0x00000B,  0x00000B }, FF_SETGRAD },
+		{"SET_GRADIENTS_V",               { 0x00000C,  0x00000C,  0x00000C,  0x00000C }, FF_SETGRAD },
+		{"SET_GRADIENTS_H_COARSE",        {       -1,        -1,        -1,  0x00010B }, FF_SETGRAD },
+		{"SET_GRADIENTS_V_COARSE",        {       -1,        -1,        -1,  0x00010C }, FF_SETGRAD },
+		{"SET_GRADIENTS_H_PACKED_FINE",   {       -1,        -1,        -1,  0x00020B }, FF_SETGRAD },
+		{"SET_GRADIENTS_V_PACKED_FINE",   {       -1,        -1,        -1,  0x00020C }, FF_SETGRAD },
+		{"SET_GRADIENTS_H_PACKED_COARSE", {       -1,        -1,        -1,  0x00030B }, FF_SETGRAD },
+		{"SET_GRADIENTS_V_PACKED_COARSE", {       -1,        -1,        -1,  0x00030C }, FF_SETGRAD },
+		{"PASS",                          { 0x00000D,  0x00000D,  0x00000D,  0x00000D }, 0 }, /* ???? 700, eg, cm docs - marked as reserved */
+		{"PASS1",                         {       -1,        -1,  0x00010D,  0x00010D }, 0 },
+		{"PASS2",                         {       -1,        -1,  0x00020D,  0x00020D }, 0 },
+		{"PASS3",                         {       -1,        -1,  0x00030D,  0x00030D }, 0 },
+		{"SET_CUBEMAP_INDEX",             { 0x00000E,  0x00000E,        -1,        -1 }, 0 },
+		{"GET_BUFFER_RESINFO",            {       -1,        -1,  0x00000E,  0x00000E }, FF_VTX },
+		{"FETCH4",                        { 0x00000F,  0x00000F,        -1,        -1 }, 0 },
+
+		{"SAMPLE",                        { 0x000010,  0x000010,  0x000010,  0x000010 }, FF_TEX },
+		{"SAMPLE_L",                      { 0x000011,  0x000011,  0x000011,  0x000011 }, FF_TEX },
+		{"SAMPLE_LB",                     { 0x000012,  0x000012,  0x000012,  0x000012 }, FF_TEX },
+		{"SAMPLE_LZ",                     { 0x000013,  0x000013,  0x000013,  0x000013 }, FF_TEX },
+		{"SAMPLE_G",                      { 0x000014,  0x000014,  0x000014,  0x000014 }, FF_TEX | FF_USEGRAD },
+		{"SAMPLE_G_L",                    { 0x000015,  0x000015,        -1,        -1 }, FF_TEX | FF_USEGRAD},
+		{"GATHER4",                       {       -1,        -1,  0x000015,  0x000015 }, FF_TEX },
+		{"SAMPLE_G_LB",                   { 0x000016,  0x000016,  0x000016,  0x000016 }, FF_TEX | FF_USEGRAD},
+		{"SAMPLE_G_LZ",                   { 0x000017,  0x000017,        -1,        -1 }, FF_TEX | FF_USEGRAD},
+		{"GATHER4_O",                     {       -1,        -1,  0x000017,  0x000017 }, FF_TEX },
+		{"SAMPLE_C",                      { 0x000018,  0x000018,  0x000018,  0x000018 }, FF_TEX },
+		{"SAMPLE_C_L",                    { 0x000019,  0x000019,  0x000019,  0x000019 }, FF_TEX },
+		{"SAMPLE_C_LB",                   { 0x00001A,  0x00001A,  0x00001A,  0x00001A }, FF_TEX },
+		{"SAMPLE_C_LZ",                   { 0x00001B,  0x00001B,  0x00001B,  0x00001B }, FF_TEX },
+		{"SAMPLE_C_G",                    { 0x00001C,  0x00001C,  0x00001C,  0x00001C }, FF_TEX | FF_USEGRAD},
+		{"SAMPLE_C_G_L",                  { 0x00001D,  0x00001D,        -1,        -1 }, FF_TEX | FF_USEGRAD},
+		{"GATHER4_C",                     {       -1,        -1,  0x00001D,  0x00001D }, FF_TEX },
+		{"SAMPLE_C_G_LB",                 { 0x00001E,  0x00001E,  0x00001E,  0x00001E }, FF_TEX | FF_USEGRAD},
+		{"SAMPLE_C_G_LZ",                 { 0x00001F,  0x00001F,        -1,        -1 }, FF_TEX | FF_USEGRAD},
+		{"GATHER4_C_O",                   {       -1,        -1,  0x00001F,  0x00001F }, FF_TEX }
+};
+
+static const struct cf_op_info cf_op_table[] = {
+		{"NOP",                           { 0x00, 0x00, 0x00, 0x00 },  0  },
+
+		{"TEX",                           { 0x01, 0x01, 0x01, 0x01 },  CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "TC" entry */
+		{"VTX",                           { 0x02, 0x02, 0x02,   -1 },  CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "VC" entry */
+		{"VTX_TC",                        { 0x03, 0x03,   -1,   -1 },  CF_CLAUSE | CF_FETCH | CF_UNCOND },
+		{"GDS",                           {   -1,   -1, 0x03, 0x03 },  CF_CLAUSE | CF_FETCH | CF_UNCOND },
+
+		{"LOOP_START",                    { 0x04, 0x04, 0x04, 0x04 },  CF_LOOP | CF_LOOP_START },
+		{"LOOP_END",                      { 0x05, 0x05, 0x05, 0x05 },  CF_LOOP  },
+		{"LOOP_START_DX10",               { 0x06, 0x06, 0x06, 0x06 },  CF_LOOP | CF_LOOP_START },
+		{"LOOP_START_NO_AL",              { 0x07, 0x07, 0x07, 0x07 },  CF_LOOP | CF_LOOP_START },
+		{"LOOP_CONTINUE",                 { 0x08, 0x08, 0x08, 0x08 },  CF_LOOP  },
+		{"LOOP_BREAK",                    { 0x09, 0x09, 0x09, 0x09 },  CF_LOOP  },
+		{"JUMP",                          { 0x0A, 0x0A, 0x0A, 0x0A },  CF_BRANCH  },
+		{"PUSH",                          { 0x0B, 0x0B, 0x0B, 0x0B },  CF_BRANCH  },
+		{"PUSH_ELSE",                     { 0x0C, 0x0C,   -1,   -1 },  CF_BRANCH  },
+		{"ELSE",                          { 0x0D, 0x0D, 0x0D, 0x0D },  CF_BRANCH  },
+		{"POP",                           { 0x0E, 0x0E, 0x0E, 0x0E },  CF_BRANCH  },
+		{"POP_JUMP",                      { 0x0F, 0x0F,   -1,   -1 },  CF_BRANCH  },
+		{"POP_PUSH",                      { 0x10, 0x10,   -1,   -1 },  CF_BRANCH  },
+		{"POP_PUSH_ELSE",                 { 0x11, 0x11,   -1,   -1 },  CF_BRANCH  },
+		{"CALL",                          { 0x12, 0x12, 0x12, 0x12 },  CF_CALL  },
+		{"CALL_FS",                       { 0x13, 0x13, 0x13, 0x13 },  CF_CALL  },
+		{"RET",                           { 0x14, 0x14, 0x14, 0x14 },  0 },
+		{"EMIT_VERTEX",                   { 0x15, 0x15, 0x15, 0x15 },  CF_EMIT | CF_UNCOND },
+		{"EMIT_CUT_VERTEX",               { 0x16, 0x16, 0x16, 0x16 },  CF_EMIT | CF_UNCOND  },
+		{"CUT_VERTEX",                    { 0x17, 0x17, 0x17, 0x17 },  CF_EMIT | CF_UNCOND  },
+		{"KILL",                          { 0x18, 0x18, 0x18, 0x18 },  CF_UNCOND  },
+		{"END_PROGRAM",                   { 0x19, 0x19, 0x19, 0x19 },  0  },  /* ??? "reserved" in isa docs */
+		{"WAIT_ACK",                      {   -1, 0x1A, 0x1A, 0x1A },  0  },
+		{"TEX_ACK",                       {   -1, 0x1B, 0x1B, 0x1B },  CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
+		{"VTX_ACK",                       {   -1, 0x1C, 0x1C,   -1 },  CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
+		{"VTX_TC_ACK",                    {   -1, 0x1D,   -1,   -1 },  CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
+		{"JUMPTABLE",                     {   -1,   -1, 0x1D, 0x1D },  CF_BRANCH  },
+		{"WAVE_SYNC",                     {   -1,   -1, 0x1E, 0x1E },  0  },
+		{"HALT",                          {   -1,   -1, 0x1F, 0x1F },  0  },
+		{"CF_END",                        {   -1,   -1,   -1, 0x20 },  0  },
+		{"LDS_DEALLOC",                   {   -1,   -1,   -1, 0x21 },  0  },
+		{"PUSH_WQM",                      {   -1,   -1,   -1, 0x22 },  CF_BRANCH  },
+		{"POP_WQM",                       {   -1,   -1,   -1, 0x23 },  CF_BRANCH  },
+		{"ELSE_WQM",                      {   -1,   -1,   -1, 0x24 },  CF_BRANCH  },
+		{"JUMP_ANY",                      {   -1,   -1,   -1, 0x25 },  CF_BRANCH  },
+
+		/* ??? next 5 added from CAYMAN ISA doc, not in the original table */
+		{"REACTIVATE",                    {   -1,   -1,   -1, 0x26 },  0  },
+		{"REACTIVATE_WQM",                {   -1,   -1,   -1, 0x27 },  0  },
+		{"INTERRUPT",                     {   -1,   -1,   -1, 0x28 },  0  },
+		{"INTERRUPT_AND_SLEEP",           {   -1,   -1,   -1, 0x29 },  0  },
+		{"SET_PRIORITY",                  {   -1,   -1,   -1, 0x2A },  0  },
+
+		{"MEM_STREAM0_BUF0",              {   -1,   -1, 0x40, 0x40 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM0_BUF1",              {   -1,   -1, 0x41, 0x41 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM0_BUF2",              {   -1,   -1, 0x42, 0x42 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM0_BUF3",              {   -1,   -1, 0x43, 0x43 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM1_BUF0",              {   -1,   -1, 0x44, 0x44 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM1_BUF1",              {   -1,   -1, 0x45, 0x45 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM1_BUF2",              {   -1,   -1, 0x46, 0x46 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM1_BUF3",              {   -1,   -1, 0x47, 0x47 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM2_BUF0",              {   -1,   -1, 0x48, 0x48 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM2_BUF1",              {   -1,   -1, 0x49, 0x49 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM2_BUF2",              {   -1,   -1, 0x4A, 0x4A },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM2_BUF3",              {   -1,   -1, 0x4B, 0x4B },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM3_BUF0",              {   -1,   -1, 0x4C, 0x4C },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM3_BUF1",              {   -1,   -1, 0x4D, 0x4D },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM3_BUF2",              {   -1,   -1, 0x4E, 0x4E },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM3_BUF3",              {   -1,   -1, 0x4F, 0x4F },  CF_MEM | CF_STRM  },
+
+		{"MEM_STREAM0",                   { 0x20, 0x20,   -1,   -1 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM1",                   { 0x21, 0x21,   -1,   -1 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM2",                   { 0x22, 0x22,   -1,   -1 },  CF_MEM | CF_STRM  },
+		{"MEM_STREAM3",                   { 0x23, 0x23,   -1,   -1 },  CF_MEM | CF_STRM  },
+
+		{"MEM_SCRATCH",                   { 0x24, 0x24, 0x50, 0x50 },  CF_MEM  },
+		{"MEM_REDUCT",                    { 0x25, 0x25,   -1,   -1 },  CF_MEM  },
+		{"MEM_RING",                      { 0x26, 0x26, 0x52, 0x52 },  CF_MEM  },
+
+		{"EXPORT",                        { 0x27, 0x27, 0x53, 0x53 },  CF_EXP  },
+		{"EXPORT_DONE",                   { 0x28, 0x28, 0x54, 0x54 },  CF_EXP  },
+
+		{"MEM_EXPORT",                    {   -1, 0x3A, 0x55, 0x55 },  CF_MEM  },
+		{"MEM_RAT",                       {   -1,   -1, 0x56, 0x56 },  CF_MEM  },
+		{"MEM_RAT_NOCACHE",               {   -1,   -1, 0x57, 0x57 },  CF_MEM  },
+		{"MEM_RING1",                     {   -1,   -1, 0x58, 0x58 },  CF_MEM  },
+		{"MEM_RING2",                     {   -1,   -1, 0x59, 0x59 },  CF_MEM  },
+		{"MEM_RING3",                     {   -1,   -1, 0x5A, 0x5A },  CF_MEM  },
+		{"MEM_MEM_COMBINED",              {   -1,   -1, 0x5B, 0x5B },  CF_MEM  },
+		{"MEM_RAT_COMBINED_NOCACHE",      {   -1,   -1, 0x5C, 0x5C },  CF_MEM  },
+		{"MEM_RAT_COMBINED",              {   -1,   -1,   -1, 0x5D },  CF_MEM  }, /* ??? not in cayman isa doc */
+
+		{"EXPORT_DONE_END",               {   -1,   -1,   -1, 0x5E },  CF_EXP  },   /* ??? not in cayman isa doc */
+
+		{"ALU",                           { 0x08, 0x08, 0x08, 0x08 },  CF_CLAUSE | CF_ALU  },
+		{"ALU_PUSH_BEFORE",               { 0x09, 0x09, 0x09, 0x09 },  CF_CLAUSE | CF_ALU  },
+		{"ALU_POP_AFTER",                 { 0x0A, 0x0A, 0x0A, 0x0A },  CF_CLAUSE | CF_ALU  },
+		{"ALU_POP2_AFTER",                { 0x0B, 0x0B, 0x0B, 0x0B },  CF_CLAUSE | CF_ALU  },
+		{"ALU_EXT",                       {   -1,   -1, 0x0C, 0x0C },  CF_CLAUSE | CF_ALU | CF_ALU_EXT  },
+		{"ALU_CONTINUE",                  { 0x0D, 0x0D, 0x0D,   -1 },  CF_CLAUSE | CF_ALU  },
+		{"ALU_BREAK",                     { 0x0E, 0x0E, 0x0E,   -1 },  CF_CLAUSE | CF_ALU  },
+		{"ALU_ELSE_AFTER",                { 0x0F, 0x0F, 0x0F, 0x0F },  CF_CLAUSE | CF_ALU  }
+};
+
+
+#define ALU_OP2_ADD                             0
+#define ALU_OP2_MUL                             1
+#define ALU_OP2_MUL_IEEE                        2
+#define ALU_OP2_MAX                             3
+#define ALU_OP2_MIN                             4
+#define ALU_OP2_MAX_DX10                        5
+#define ALU_OP2_MIN_DX10                        6
+#define ALU_OP2_SETE                            7
+#define ALU_OP2_SETGT                           8
+#define ALU_OP2_SETGE                           9
+#define ALU_OP2_SETNE                          10
+#define ALU_OP2_SETE_DX10                      11
+#define ALU_OP2_SETGT_DX10                     12
+#define ALU_OP2_SETGE_DX10                     13
+#define ALU_OP2_SETNE_DX10                     14
+#define ALU_OP1_FRACT                          15
+#define ALU_OP1_TRUNC                          16
+#define ALU_OP1_CEIL                           17
+#define ALU_OP1_RNDNE                          18
+#define ALU_OP1_FLOOR                          19
+#define ALU_OP2_ASHR_INT                       20
+#define ALU_OP2_LSHR_INT                       21
+#define ALU_OP2_LSHL_INT                       22
+#define ALU_OP1_MOV                            23
+#define ALU_OP0_NOP                            24
+#define ALU_OP2_PRED_SETGT_UINT                25
+#define ALU_OP2_PRED_SETGE_UINT                26
+#define ALU_OP2_PRED_SETE                      27
+#define ALU_OP2_PRED_SETGT                     28
+#define ALU_OP2_PRED_SETGE                     29
+#define ALU_OP2_PRED_SETNE                     30
+#define ALU_OP1_PRED_SET_INV                   31
+#define ALU_OP2_PRED_SET_POP                   32
+#define ALU_OP0_PRED_SET_CLR                   33
+#define ALU_OP1_PRED_SET_RESTORE               34
+#define ALU_OP2_PRED_SETE_PUSH                 35
+#define ALU_OP2_PRED_SETGT_PUSH                36
+#define ALU_OP2_PRED_SETGE_PUSH                37
+#define ALU_OP2_PRED_SETNE_PUSH                38
+#define ALU_OP2_KILLE                          39
+#define ALU_OP2_KILLGT                         40
+#define ALU_OP2_KILLGE                         41
+#define ALU_OP2_KILLNE                         42
+#define ALU_OP2_AND_INT                        43
+#define ALU_OP2_OR_INT                         44
+#define ALU_OP2_XOR_INT                        45
+#define ALU_OP1_NOT_INT                        46
+#define ALU_OP2_ADD_INT                        47
+#define ALU_OP2_SUB_INT                        48
+#define ALU_OP2_MAX_INT                        49
+#define ALU_OP2_MIN_INT                        50
+#define ALU_OP2_MAX_UINT                       51
+#define ALU_OP2_MIN_UINT                       52
+#define ALU_OP2_SETE_INT                       53
+#define ALU_OP2_SETGT_INT                      54
+#define ALU_OP2_SETGE_INT                      55
+#define ALU_OP2_SETNE_INT                      56
+#define ALU_OP2_SETGT_UINT                     57
+#define ALU_OP2_SETGE_UINT                     58
+#define ALU_OP2_KILLGT_UINT                    59
+#define ALU_OP2_KILLGE_UINT                    60
+#define ALU_OP2_PRED_SETE_INT                  61
+#define ALU_OP2_PRED_SETGT_INT                 62
+#define ALU_OP2_PRED_SETGE_INT                 63
+#define ALU_OP2_PRED_SETNE_INT                 64
+#define ALU_OP2_KILLE_INT                      65
+#define ALU_OP2_KILLGT_INT                     66
+#define ALU_OP2_KILLGE_INT                     67
+#define ALU_OP2_KILLNE_INT                     68
+#define ALU_OP2_PRED_SETE_PUSH_INT             69
+#define ALU_OP2_PRED_SETGT_PUSH_INT            70
+#define ALU_OP2_PRED_SETGE_PUSH_INT            71
+#define ALU_OP2_PRED_SETNE_PUSH_INT            72
+#define ALU_OP2_PRED_SETLT_PUSH_INT            73
+#define ALU_OP2_PRED_SETLE_PUSH_INT            74
+#define ALU_OP1_FLT_TO_INT                     75
+#define ALU_OP1_BFREV_INT                      76
+#define ALU_OP2_ADDC_UINT                      77
+#define ALU_OP2_SUBB_UINT                      78
+#define ALU_OP0_GROUP_BARRIER                  79
+#define ALU_OP0_GROUP_SEQ_BEGIN                80
+#define ALU_OP0_GROUP_SEQ_END                  81
+#define ALU_OP2_SET_MODE                       82
+#define ALU_OP0_SET_CF_IDX0                    83
+#define ALU_OP0_SET_CF_IDX1                    84
+#define ALU_OP2_SET_LDS_SIZE                   85
+#define ALU_OP2_MUL_INT24                      86
+#define ALU_OP2_MULHI_INT24                    87
+#define ALU_OP1_FLT_TO_INT_TRUNC               88
+#define ALU_OP1_EXP_IEEE                       89
+#define ALU_OP1_LOG_CLAMPED                    90
+#define ALU_OP1_LOG_IEEE                       91
+#define ALU_OP1_RECIP_CLAMPED                  92
+#define ALU_OP1_RECIP_FF                       93
+#define ALU_OP1_RECIP_IEEE                     94
+#define ALU_OP1_RECIPSQRT_CLAMPED              95
+#define ALU_OP1_RECIPSQRT_FF                   96
+#define ALU_OP1_RECIPSQRT_IEEE                 97
+#define ALU_OP1_SQRT_IEEE                      98
+#define ALU_OP1_SIN                            99
+#define ALU_OP1_COS                           100
+#define ALU_OP2_MULLO_INT                     101
+#define ALU_OP2_MULHI_INT                     102
+#define ALU_OP2_MULLO_UINT                    103
+#define ALU_OP2_MULHI_UINT                    104
+#define ALU_OP1_RECIP_INT                     105
+#define ALU_OP1_RECIP_UINT                    106
+#define ALU_OP2_RECIP_64                      107
+#define ALU_OP2_RECIP_CLAMPED_64              108
+#define ALU_OP2_RECIPSQRT_64                  109
+#define ALU_OP2_RECIPSQRT_CLAMPED_64          110
+#define ALU_OP2_SQRT_64                       111
+#define ALU_OP1_FLT_TO_UINT                   112
+#define ALU_OP1_INT_TO_FLT                    113
+#define ALU_OP1_UINT_TO_FLT                   114
+#define ALU_OP2_BFM_INT                       115
+#define ALU_OP1_FLT32_TO_FLT16                116
+#define ALU_OP1_FLT16_TO_FLT32                117
+#define ALU_OP1_UBYTE0_FLT                    118
+#define ALU_OP1_UBYTE1_FLT                    119
+#define ALU_OP1_UBYTE2_FLT                    120
+#define ALU_OP1_UBYTE3_FLT                    121
+#define ALU_OP1_BCNT_INT                      122
+#define ALU_OP1_FFBH_UINT                     123
+#define ALU_OP1_FFBL_INT                      124
+#define ALU_OP1_FFBH_INT                      125
+#define ALU_OP1_FLT_TO_UINT4                  126
+#define ALU_OP2_DOT_IEEE                      127
+#define ALU_OP1_FLT_TO_INT_RPI                128
+#define ALU_OP1_FLT_TO_INT_FLOOR              129
+#define ALU_OP2_MULHI_UINT24                  130
+#define ALU_OP1_MBCNT_32HI_INT                131
+#define ALU_OP1_OFFSET_TO_FLT                 132
+#define ALU_OP2_MUL_UINT24                    133
+#define ALU_OP1_BCNT_ACCUM_PREV_INT           134
+#define ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT     135
+#define ALU_OP2_SETE_64                       136
+#define ALU_OP2_SETNE_64                      137
+#define ALU_OP2_SETGT_64                      138
+#define ALU_OP2_SETGE_64                      139
+#define ALU_OP2_MIN_64                        140
+#define ALU_OP2_MAX_64                        141
+#define ALU_OP2_DOT4                          142
+#define ALU_OP2_DOT4_IEEE                     143
+#define ALU_OP2_CUBE                          144
+#define ALU_OP1_MAX4                          145
+#define ALU_OP1_FREXP_64                      146
+#define ALU_OP2_LDEXP_64                      147
+#define ALU_OP1_FRACT_64                      148
+#define ALU_OP2_PRED_SETGT_64                 149
+#define ALU_OP2_PRED_SETE_64                  150
+#define ALU_OP2_PRED_SETGE_64                 151
+#define ALU_OP2_MUL_64                        152
+#define ALU_OP2_ADD_64                        153
+#define ALU_OP1_MOVA_INT                      154
+#define ALU_OP1_FLT64_TO_FLT32                155
+#define ALU_OP1_FLT32_TO_FLT64                156
+#define ALU_OP2_SAD_ACCUM_PREV_UINT           157
+#define ALU_OP2_DOT                           158
+#define ALU_OP1_MUL_PREV                      159
+#define ALU_OP1_MUL_IEEE_PREV                 160
+#define ALU_OP1_ADD_PREV                      161
+#define ALU_OP2_MULADD_PREV                   162
+#define ALU_OP2_MULADD_IEEE_PREV              163
+#define ALU_OP2_INTERP_XY                     164
+#define ALU_OP2_INTERP_ZW                     165
+#define ALU_OP2_INTERP_X                      166
+#define ALU_OP2_INTERP_Z                      167
+#define ALU_OP1_STORE_FLAGS                   168
+#define ALU_OP1_LOAD_STORE_FLAGS              169
+#define ALU_OP2_LDS_1A                        170
+#define ALU_OP2_LDS_1A1D                      171
+#define ALU_OP2_LDS_2A                        172
+#define ALU_OP1_INTERP_LOAD_P0                173
+#define ALU_OP1_INTERP_LOAD_P10               174
+#define ALU_OP1_INTERP_LOAD_P20               175
+#define ALU_OP3_BFE_UINT                      176
+#define ALU_OP3_BFE_INT                       177
+#define ALU_OP3_BFI_INT                       178
+#define ALU_OP3_FMA                           179
+#define ALU_OP3_MULADD_INT24                  180
+#define ALU_OP3_CNDNE_64                      181
+#define ALU_OP3_FMA_64                        182
+#define ALU_OP3_LERP_UINT                     183
+#define ALU_OP3_BIT_ALIGN_INT                 184
+#define ALU_OP3_BYTE_ALIGN_INT                185
+#define ALU_OP3_SAD_ACCUM_UINT                186
+#define ALU_OP3_SAD_ACCUM_HI_UINT             187
+#define ALU_OP3_MULADD_UINT24                 188
+#define ALU_OP3_LDS_IDX_OP                    189
+#define ALU_OP3_MULADD                        190
+#define ALU_OP3_MULADD_M2                     191
+#define ALU_OP3_MULADD_M4                     192
+#define ALU_OP3_MULADD_D2                     193
+#define ALU_OP3_MULADD_IEEE                   194
+#define ALU_OP3_CNDE                          195
+#define ALU_OP3_CNDGT                         196
+#define ALU_OP3_CNDGE                         197
+#define ALU_OP3_CNDE_INT                      198
+#define ALU_OP3_CNDGT_INT                     199
+#define ALU_OP3_CNDGE_INT                     200
+#define ALU_OP3_MUL_LIT                       201
+#define ALU_OP1_MOVA                          202
+#define ALU_OP1_MOVA_FLOOR                    203
+#define ALU_OP1_MOVA_GPR_INT                  204
+#define ALU_OP3_MULADD_64                     205
+#define ALU_OP3_MULADD_64_M2                  206
+#define ALU_OP3_MULADD_64_M4                  207
+#define ALU_OP3_MULADD_64_D2                  208
+#define ALU_OP3_MUL_LIT_M2                    209
+#define ALU_OP3_MUL_LIT_M4                    210
+#define ALU_OP3_MUL_LIT_D2                    211
+#define ALU_OP3_MULADD_IEEE_M2                212
+#define ALU_OP3_MULADD_IEEE_M4                213
+#define ALU_OP3_MULADD_IEEE_D2                214
+
+#define LDS_OP2_LDS_ADD                       215
+#define LDS_OP2_LDS_SUB                       216
+#define LDS_OP2_LDS_RSUB                      217
+#define LDS_OP2_LDS_INC                       218
+#define LDS_OP2_LDS_DEC                       219
+#define LDS_OP2_LDS_MIN_INT                   220
+#define LDS_OP2_LDS_MAX_INT                   221
+#define LDS_OP2_LDS_MIN_UINT                  222
+#define LDS_OP2_LDS_MAX_UINT                  223
+#define LDS_OP2_LDS_AND                       224
+#define LDS_OP2_LDS_OR                        225
+#define LDS_OP2_LDS_XOR                       226
+#define LDS_OP3_LDS_MSKOR                     227
+#define LDS_OP2_LDS_WRITE                     228
+#define LDS_OP3_LDS_WRITE_REL                 229
+#define LDS_OP3_LDS_WRITE2                    230
+#define LDS_OP3_LDS_CMP_STORE                 231
+#define LDS_OP3_LDS_CMP_STORE_SPF             232
+#define LDS_OP2_LDS_BYTE_WRITE                233
+#define LDS_OP2_LDS_SHORT_WRITE               234
+#define LDS_OP2_LDS_ADD_RET                   235
+#define LDS_OP2_LDS_SUB_RET                   236
+#define LDS_OP2_LDS_RSUB_RET                  237
+#define LDS_OP2_LDS_INC_RET                   238
+#define LDS_OP2_LDS_DEC_RET                   239
+#define LDS_OP2_LDS_MIN_INT_RET               240
+#define LDS_OP2_LDS_MAX_INT_RET               241
+#define LDS_OP2_LDS_MIN_UINT_RET              242
+#define LDS_OP2_LDS_MAX_UINT_RET              243
+#define LDS_OP2_LDS_AND_RET                   244
+#define LDS_OP2_LDS_OR_RET                    245
+#define LDS_OP2_LDS_XOR_RET                   246
+#define LDS_OP3_LDS_MSKOR_RET                 247
+#define LDS_OP2_LDS_XCHG_RET                  248
+#define LDS_OP3_LDS_XCHG_REL_RET              249
+#define LDS_OP3_LDS_XCHG2_RET                 250
+#define LDS_OP3_LDS_CMP_XCHG_RET              251
+#define LDS_OP3_LDS_CMP_XCHG_SPF_RET          252
+#define LDS_OP1_LDS_READ_RET                  253
+#define LDS_OP1_LDS_READ_REL_RET              254
+#define LDS_OP2_LDS_READ2_RET                 255
+#define LDS_OP3_LDS_READWRITE_RET             256
+#define LDS_OP1_LDS_BYTE_READ_RET             257
+#define LDS_OP1_LDS_UBYTE_READ_RET            258
+#define LDS_OP1_LDS_SHORT_READ_RET            259
+#define LDS_OP1_LDS_USHORT_READ_RET           260
+
+#define FETCH_OP_VFETCH                           0
+#define FETCH_OP_SEMFETCH                         1
+#define FETCH_OP_READ_SCRATCH                     2
+#define FETCH_OP_READ_REDUCT                      3
+#define FETCH_OP_READ_MEM                         4
+#define FETCH_OP_DS_LOCAL_WRITE                   5
+#define FETCH_OP_DS_LOCAL_READ                    6
+#define FETCH_OP_GDS_ADD                          7
+#define FETCH_OP_GDS_SUB                          8
+#define FETCH_OP_GDS_RSUB                         9
+#define FETCH_OP_GDS_INC                         10
+#define FETCH_OP_GDS_DEC                         11
+#define FETCH_OP_GDS_MIN_INT                     12
+#define FETCH_OP_GDS_MAX_INT                     13
+#define FETCH_OP_GDS_MIN_UINT                    14
+#define FETCH_OP_GDS_MAX_UINT                    15
+#define FETCH_OP_GDS_AND                         16
+#define FETCH_OP_GDS_OR                          17
+#define FETCH_OP_GDS_XOR                         18
+#define FETCH_OP_GDS_MSKOR                       19
+#define FETCH_OP_GDS_WRITE                       20
+#define FETCH_OP_GDS_WRITE_REL                   21
+#define FETCH_OP_GDS_WRITE2                      22
+#define FETCH_OP_GDS_CMP_STORE                   23
+#define FETCH_OP_GDS_CMP_STORE_SPF               24
+#define FETCH_OP_GDS_BYTE_WRITE                  25
+#define FETCH_OP_GDS_SHORT_WRITE                 26
+#define FETCH_OP_GDS_ADD_RET                     27
+#define FETCH_OP_GDS_SUB_RET                     28
+#define FETCH_OP_GDS_RSUB_RET                    29
+#define FETCH_OP_GDS_INC_RET                     30
+#define FETCH_OP_GDS_DEC_RET                     31
+#define FETCH_OP_GDS_MIN_INT_RET                 32
+#define FETCH_OP_GDS_MAX_INT_RET                 33
+#define FETCH_OP_GDS_MIN_UINT_RET                34
+#define FETCH_OP_GDS_MAX_UINT_RET                35
+#define FETCH_OP_GDS_AND_RET                     36
+#define FETCH_OP_GDS_OR_RET                      37
+#define FETCH_OP_GDS_XOR_RET                     38
+#define FETCH_OP_GDS_MSKOR_RET                   39
+#define FETCH_OP_GDS_XCHG_RET                    40
+#define FETCH_OP_GDS_XCHG_REL_RET                41
+#define FETCH_OP_GDS_XCHG2_RET                   42
+#define FETCH_OP_GDS_CMP_XCHG_RET                43
+#define FETCH_OP_GDS_CMP_XCHG_SPF_RET            44
+#define FETCH_OP_GDS_READ_RET                    45
+#define FETCH_OP_GDS_READ_REL_RET                46
+#define FETCH_OP_GDS_READ2_RET                   47
+#define FETCH_OP_GDS_READWRITE_RET               48
+#define FETCH_OP_GDS_BYTE_READ_RET               49
+#define FETCH_OP_GDS_UBYTE_READ_RET              50
+#define FETCH_OP_GDS_SHORT_READ_RET              51
+#define FETCH_OP_GDS_USHORT_READ_RET             52
+#define FETCH_OP_GDS_ATOMIC_ORDERED_ALLOC        53
+#define FETCH_OP_TF_WRITE                        54
+#define FETCH_OP_DS_GLOBAL_WRITE                 55
+#define FETCH_OP_DS_GLOBAL_READ                  56
+#define FETCH_OP_LD                              57
+#define FETCH_OP_LDFPTR                          58
+#define FETCH_OP_GET_TEXTURE_RESINFO             59
+#define FETCH_OP_GET_NUMBER_OF_SAMPLES           60
+#define FETCH_OP_GET_LOD                         61
+#define FETCH_OP_GET_GRADIENTS_H                 62
+#define FETCH_OP_GET_GRADIENTS_V                 63
+#define FETCH_OP_GET_GRADIENTS_H_FINE            64
+#define FETCH_OP_GET_GRADIENTS_V_FINE            65
+#define FETCH_OP_GET_LERP                        66
+#define FETCH_OP_SET_TEXTURE_OFFSETS             67
+#define FETCH_OP_KEEP_GRADIENTS                  68
+#define FETCH_OP_SET_GRADIENTS_H                 69
+#define FETCH_OP_SET_GRADIENTS_V                 70
+#define FETCH_OP_SET_GRADIENTS_H_COARSE          71
+#define FETCH_OP_SET_GRADIENTS_V_COARSE          72
+#define FETCH_OP_SET_GRADIENTS_H_PACKED_FINE     73
+#define FETCH_OP_SET_GRADIENTS_V_PACKED_FINE     74
+#define FETCH_OP_SET_GRADIENTS_H_PACKED_COARSE   75
+#define FETCH_OP_SET_GRADIENTS_V_PACKED_COARSE   76
+#define FETCH_OP_PASS                            77
+#define FETCH_OP_PASS1                           78
+#define FETCH_OP_PASS2                           79
+#define FETCH_OP_PASS3                           80
+#define FETCH_OP_SET_CUBEMAP_INDEX               81
+#define FETCH_OP_GET_BUFFER_RESINFO              82
+#define FETCH_OP_FETCH4                          83
+#define FETCH_OP_SAMPLE                          84
+#define FETCH_OP_SAMPLE_L                        85
+#define FETCH_OP_SAMPLE_LB                       86
+#define FETCH_OP_SAMPLE_LZ                       87
+#define FETCH_OP_SAMPLE_G                        88
+#define FETCH_OP_SAMPLE_G_L                      89
+#define FETCH_OP_GATHER4                         90
+#define FETCH_OP_SAMPLE_G_LB                     91
+#define FETCH_OP_SAMPLE_G_LZ                     92
+#define FETCH_OP_GATHER4_O                       93
+#define FETCH_OP_SAMPLE_C                        94
+#define FETCH_OP_SAMPLE_C_L                      95
+#define FETCH_OP_SAMPLE_C_LB                     96
+#define FETCH_OP_SAMPLE_C_LZ                     97
+#define FETCH_OP_SAMPLE_C_G                      98
+#define FETCH_OP_SAMPLE_C_G_L                    99
+#define FETCH_OP_GATHER4_C                      100
+#define FETCH_OP_SAMPLE_C_G_LB                  101
+#define FETCH_OP_SAMPLE_C_G_LZ                  102
+#define FETCH_OP_GATHER4_C_O                    103
+
+#define CF_OP_NOP                           0
+#define CF_OP_TEX                           1
+#define CF_OP_VTX                           2
+#define CF_OP_VTX_TC                        3
+#define CF_OP_GDS                           4
+#define CF_OP_LOOP_START                    5
+#define CF_OP_LOOP_END                      6
+#define CF_OP_LOOP_START_DX10               7
+#define CF_OP_LOOP_START_NO_AL              8
+#define CF_OP_LOOP_CONTINUE                 9
+#define CF_OP_LOOP_BREAK                   10
+#define CF_OP_JUMP                         11
+#define CF_OP_PUSH                         12
+#define CF_OP_PUSH_ELSE                    13
+#define CF_OP_ELSE                         14
+#define CF_OP_POP                          15
+#define CF_OP_POP_JUMP                     16
+#define CF_OP_POP_PUSH                     17
+#define CF_OP_POP_PUSH_ELSE                18
+#define CF_OP_CALL                         19
+#define CF_OP_CALL_FS                      20
+#define CF_OP_RET                          21
+#define CF_OP_EMIT_VERTEX                  22
+#define CF_OP_EMIT_CUT_VERTEX              23
+#define CF_OP_CUT_VERTEX                   24
+#define CF_OP_KILL                         25
+#define CF_OP_END_PROGRAM                  26
+#define CF_OP_WAIT_ACK                     27
+#define CF_OP_TEX_ACK                      28
+#define CF_OP_VTX_ACK                      29
+#define CF_OP_VTX_TC_ACK                   30
+#define CF_OP_JUMPTABLE                    31
+#define CF_OP_WAVE_SYNC                    32
+#define CF_OP_HALT                         33
+#define CF_OP_CF_END                       34
+#define CF_OP_LDS_DEALLOC                  35
+#define CF_OP_PUSH_WQM                     36
+#define CF_OP_POP_WQM                      37
+#define CF_OP_ELSE_WQM                     38
+#define CF_OP_JUMP_ANY                     39
+#define CF_OP_REACTIVATE                   40
+#define CF_OP_REACTIVATE_WQM               41
+#define CF_OP_INTERRUPT                    42
+#define CF_OP_INTERRUPT_AND_SLEEP          43
+#define CF_OP_SET_PRIORITY                 44
+#define CF_OP_MEM_STREAM0_BUF0             45
+#define CF_OP_MEM_STREAM0_BUF1             46
+#define CF_OP_MEM_STREAM0_BUF2             47
+#define CF_OP_MEM_STREAM0_BUF3             48
+#define CF_OP_MEM_STREAM1_BUF0             49
+#define CF_OP_MEM_STREAM1_BUF1             50
+#define CF_OP_MEM_STREAM1_BUF2             51
+#define CF_OP_MEM_STREAM1_BUF3             52
+#define CF_OP_MEM_STREAM2_BUF0             53
+#define CF_OP_MEM_STREAM2_BUF1             54
+#define CF_OP_MEM_STREAM2_BUF2             55
+#define CF_OP_MEM_STREAM2_BUF3             56
+#define CF_OP_MEM_STREAM3_BUF0             57
+#define CF_OP_MEM_STREAM3_BUF1             58
+#define CF_OP_MEM_STREAM3_BUF2             59
+#define CF_OP_MEM_STREAM3_BUF3             60
+#define CF_OP_MEM_STREAM0                  61
+#define CF_OP_MEM_STREAM1                  62
+#define CF_OP_MEM_STREAM2                  63
+#define CF_OP_MEM_STREAM3                  64
+#define CF_OP_MEM_SCRATCH                  65
+#define CF_OP_MEM_REDUCT                   66
+#define CF_OP_MEM_RING                     67
+#define CF_OP_EXPORT                       68
+#define CF_OP_EXPORT_DONE                  69
+#define CF_OP_MEM_EXPORT                   70
+#define CF_OP_MEM_RAT                      71
+#define CF_OP_MEM_RAT_NOCACHE              72
+#define CF_OP_MEM_RING1                    73
+#define CF_OP_MEM_RING2                    74
+#define CF_OP_MEM_RING3                    75
+#define CF_OP_MEM_MEM_COMBINED             76
+#define CF_OP_MEM_RAT_COMBINED_NOCACHE     77
+#define CF_OP_MEM_RAT_COMBINED             78
+#define CF_OP_EXPORT_DONE_END              79
+#define CF_OP_ALU                          80
+#define CF_OP_ALU_PUSH_BEFORE              81
+#define CF_OP_ALU_POP_AFTER                82
+#define CF_OP_ALU_POP2_AFTER               83
+#define CF_OP_ALU_EXT                      84
+#define CF_OP_ALU_CONTINUE                 85
+#define CF_OP_ALU_BREAK                    86
+#define CF_OP_ALU_ELSE_AFTER               87
+
+/* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */
+#define CF_NATIVE							(-1)
+
+enum r600_chip_class {
+	ISA_CC_R600,
+	ISA_CC_R700,
+	ISA_CC_EVERGREEN,
+	ISA_CC_CAYMAN
+};
+
+struct r600_isa {
+	enum r600_chip_class hw_class;
+
+	/* these arrays provide reverse mapping - opcode => table_index,
+	 * typically we don't need such lookup, unless we are decoding the native
+	 * bytecode (e.g. when reading the bytestream from llvm backend) */
+	unsigned *alu_op2_map;
+	unsigned *alu_op3_map;
+	unsigned *fetch_map;
+	unsigned *cf_map;
+};
+
+struct r600_context;
+
+int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa);
+int r600_isa_destroy(struct r600_isa *isa);
+
+#define TABLE_SIZE(t) (sizeof(t)/sizeof(t[0]))
+
+static inline const struct alu_op_info *
+r600_isa_alu(unsigned op) {
+	assert (op < TABLE_SIZE(alu_op_table));
+	return &alu_op_table[op];
+}
+
+static inline const struct fetch_op_info *
+r600_isa_fetch(unsigned op) {
+	assert (op < TABLE_SIZE(fetch_op_table));
+	return &fetch_op_table[op];
+}
+
+static inline const struct cf_op_info *
+r600_isa_cf(unsigned op) {
+	assert (op < TABLE_SIZE(cf_op_table));
+	return &cf_op_table[op];
+}
+
+static inline unsigned
+r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {
+	int opc =  r600_isa_alu(op)->opcode[chip_class >> 1];
+	assert(opc != -1);
+	return opc;
+}
+
+static inline unsigned
+r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) {
+	unsigned slots = r600_isa_alu(op)->slots[chip_class];
+	assert(slots != 0);
+	return slots;
+}
+
+static inline unsigned
+r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) {
+	int opc = r600_isa_fetch(op)->opcode[chip_class];
+	assert(opc != -1);
+	return opc;
+}
+
+static inline unsigned
+r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {
+	int opc = r600_isa_cf(op)->opcode[chip_class];
+	assert(opc != -1);
+	return opc;
+}
+
+static inline unsigned
+r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {
+	unsigned op;
+	if (is_op3) {
+		assert(isa->alu_op3_map);
+		op = isa->alu_op3_map[opcode];
+	} else {
+		assert(isa->alu_op2_map);
+		op = isa->alu_op2_map[opcode];
+	}
+	assert(op);
+	return op - 1;
+}
+
+static inline unsigned
+r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {
+	unsigned op;
+	assert(isa->fetch_map);
+	op = isa->fetch_map[opcode];
+	assert(op);
+	return op - 1;
+}
+
+static inline unsigned
+r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {
+	unsigned op;
+	assert(isa->cf_map);
+	/* using offset for CF_ALU_xxx opcodes because they overlap with other
+	 * CF opcodes (they use different encoding in hw) */
+	op = isa->cf_map[is_alu ? opcode + 0x80 : opcode];
+	assert(op);
+	return op - 1;
+}
+
+#endif /* R600_ISA_H_ */
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index a59578db9c4..73a8d1aa81d 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -22,6 +22,7 @@
  */
 #include "r600_pipe.h"
 #include "r600_public.h"
+#include "r600_isa.h"
 
 #include <errno.h>
 #include "pipe/p_shader_tokens.h"
@@ -260,6 +261,8 @@ static void r600_destroy_context(struct pipe_context *context)
 {
 	struct r600_context *rctx = (struct r600_context *)context;
 
+	r600_isa_destroy(rctx->isa);
+
 	pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 	pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 
@@ -419,7 +422,11 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 
 	rctx->allocator_so_filled_size = u_suballocator_create(&rctx->context, 4096, 4,
 								0, PIPE_USAGE_STATIC, TRUE);
-        if (!rctx->allocator_so_filled_size)
+	if (!rctx->allocator_so_filled_size)
+		goto fail;
+
+	rctx->isa = calloc(1, sizeof(struct r600_isa));
+	if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 		goto fail;
 
 	rctx->blitter = util_blitter_create(&rctx->context);
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index ec59c929524..de9c205cf7b 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -552,6 +552,8 @@ struct r600_context {
 	struct list_head		dirty;
 	struct list_head		enable_list;
 	unsigned			pm4_dirty_cdwords;
+
+	struct r600_isa		*isa;
 };
 
 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index e8992ba5bed..f30ca42c16f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -137,6 +137,8 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 	struct r600_pipe_shader_selector *sel = shader->selector;
 	int r;
 
+	shader->shader.bc.isa = rctx->isa;
+
 	/* Would like some magic "get_bool_option_once" routine.
 	*/
 	if (dump_shaders == -1)
@@ -219,7 +221,7 @@ struct r600_shader_ctx {
 struct r600_shader_tgsi_instruction {
 	unsigned	tgsi_opcode;
 	unsigned	is_op3;
-	unsigned	r600_opcode;
+	unsigned	op;
 	int (*process)(struct r600_shader_ctx *ctx);
 };
 
@@ -312,6 +314,7 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 	unsigned src_idx, src_num;
 	struct r600_bytecode_alu alu;
 	unsigned src_use_sel[3];
+	const struct alu_op_info *alu_op;
 	unsigned src_sel[3] = {};
 	uint32_t word0, word1;
 
@@ -335,12 +338,12 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 	switch(ctx->bc->chip_class) {
 	default:
 	case R600:
-		r600_bytecode_alu_read(&alu, word0, word1);
+		r600_bytecode_alu_read(ctx->bc, &alu, word0, word1);
 		break;
 	case R700:
 	case EVERGREEN:
 	case CAYMAN:
-		r700_bytecode_alu_read(&alu, word0, word1);
+		r700_bytecode_alu_read(ctx->bc, &alu, word0, word1);
 		break;
 	}
 
@@ -362,11 +365,10 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 		}
 	}
 
+	alu_op = r600_isa_alu(alu.op);
+
 #if HAVE_LLVM < 0x0302
-	if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE) ||
-	    alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE) ||
-	    alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT) ||
-	    alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT)) {
+	if ((alu_op->flags & AF_PRED) && alu_op->src_count == 2) {
 		alu.update_pred = 1;
 		alu.dst.write = 0;
 		alu.src[1].sel = V_SQ_ALU_SRC_0;
@@ -375,7 +377,7 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 	}
 #endif
 
-	if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT)) {
+	if (alu_op->flags & AF_MOVA) {
 		ctx->bc->ar_reg = alu.src[0].sel;
 		ctx->bc->ar_chan = alu.src[0].chan;
 		ctx->bc->ar_loaded = 0;
@@ -384,13 +386,13 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 
 	if (alu.execute_mask) {
 		alu.pred_sel = 0;
-		r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
+		r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
 	} else {
 		r600_bytecode_add_alu(ctx->bc, &alu);
 	}
 
 	/* XXX: Handle other KILL instructions */
-	if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT)) {
+	if (alu_op->flags & AF_KILL) {
 		ctx->shader->uses_kill = 1;
 		/* XXX: This should be enforced in the LLVM backend. */
 		ctx->bc->force_add_cf = 1;
@@ -400,7 +402,7 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 
 static void llvm_if(struct r600_shader_ctx *ctx)
 {
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
 	fc_pushlevel(ctx, FC_IF);
 	callstack_check_depth(ctx, FC_PUSH_VPM, 0);
 }
@@ -472,7 +474,7 @@ static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
 {
 	struct r600_bytecode_tex tex;
 
-	tex.inst = bytes[bytes_read++];
+	tex.op = r600_isa_fetch_by_opcode(ctx->bc->isa, bytes[bytes_read++]);
 	tex.resource_id = bytes[bytes_read++];
 	tex.src_gpr = bytes[bytes_read++];
 	tex.src_rel = bytes[bytes_read++];
@@ -515,7 +517,8 @@ static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
 	memset(&vtx, 0, sizeof(vtx));
 
 	/* WORD0 */
-	vtx.inst = G_SQ_VTX_WORD0_VTX_INST(word0);
+	vtx.op = r600_isa_fetch_by_opcode(ctx->bc->isa,
+			G_SQ_VTX_WORD0_VTX_INST(word0));
 	vtx.fetch_type = G_SQ_VTX_WORD0_FETCH_TYPE(word0);
 	vtx.buffer_id = G_SQ_VTX_WORD0_BUFFER_ID(word0);
 	vtx.src_gpr = G_SQ_VTX_WORD0_SRC_GPR(word0);
@@ -545,7 +548,7 @@ static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
 	/* Use the Texture Cache for compute shaders*/
 	if (ctx->bc->chip_class >= EVERGREEN &&
 		ctx->bc->type == TGSI_PROCESSOR_COMPUTE) {
-		ctx->bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX;
+		ctx->bc->cf_last->op = CF_OP_TEX;
 	}
 	return bytes_read;
 }
@@ -559,9 +562,9 @@ static int r600_export_from_byte_stream(struct r600_shader_ctx *ctx,
 	word0 = i32_from_byte_stream(bytes, &bytes_read);
 	word1 = i32_from_byte_stream(bytes, &bytes_read);
 	if (ctx->bc->chip_class >= EVERGREEN)
-		eg_bytecode_export_read(&output, word0,word1);
+		eg_bytecode_export_read(ctx->bc, &output, word0,word1);
 	else
-		r600_bytecode_export_read(&output, word0,word1);
+		r600_bytecode_export_read(ctx->bc, &output, word0,word1);
 	r600_bytecode_add_output(ctx->bc, &output);
 	return bytes_read;
 }
@@ -688,9 +691,9 @@ static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
 		if (i < 4)
-			alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW;
+			alu.op = ALU_OP2_INTERP_ZW;
 		else
-			alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY;
+			alu.op = ALU_OP2_INTERP_XY;
 
 		if ((i > 1) && (i < 6)) {
 			alu.dst.sel = ctx->shader->input[input].gpr;
@@ -722,7 +725,7 @@ static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0;
+		alu.op = ALU_OP1_INTERP_LOAD_P0;
 
 		alu.dst.sel = ctx->shader->input[input].gpr;
 		alu.dst.write = 1;
@@ -833,7 +836,7 @@ static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back
 
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
+		alu.op = ALU_OP3_CNDGT;
 		alu.is_op3 = 1;
 		alu.dst.write = 1;
 		alu.dst.sel = gpr_front;
@@ -928,7 +931,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 				struct r600_bytecode_alu alu;
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
+				alu.op = ALU_OP1_INT_TO_FLT;
 				alu.src[0].sel = 0;
 				alu.src[0].chan = 3;
 
@@ -1066,7 +1069,7 @@ static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx
 
 		memset(&alu, 0, sizeof(alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
+		alu.op = ALU_OP2_ADD_INT;
 		alu.src[0].sel = ctx->bc->ar_reg;
 
 		alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -1136,7 +1139,7 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx)
 			int treg = r600_get_temp(ctx);
 			for (k = 0; k < 4; k++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+				alu.op = ALU_OP1_MOV;
 				alu.src[0].sel = ctx->src[i].sel;
 				alu.src[0].chan = k;
 				alu.src[0].rel = ctx->src[i].rel;
@@ -1174,7 +1177,7 @@ static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
 			int treg = r600_get_temp(ctx);
 			for (k = 0; k < 4; k++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+				alu.op = ALU_OP1_MOV;
 				alu.src[0].sel = ctx->src[i].sel;
 				alu.src[0].chan = k;
 				alu.src[0].value = ctx->src[i].value[k];
@@ -1280,11 +1283,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 	}
 	if (ctx.type == TGSI_PROCESSOR_VERTEX) {
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
-		if (ctx.bc->chip_class >= EVERGREEN) {
-			r600_bytecode_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
-		} else {
-			r600_bytecode_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
-		}
+		r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
 	}
 	if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
 		ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
@@ -1450,7 +1449,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 				for (j = 0 ; j < 4; j++) {
 					struct r600_bytecode_alu alu;
 					memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-					alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+					alu.op = ALU_OP1_RECIP_IEEE;
 					alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
 					alu.src[0].chan = 3;
 
@@ -1464,7 +1463,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 			} else {
 				struct r600_bytecode_alu alu;
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+				alu.op = ALU_OP1_RECIP_IEEE;
 				alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
 				alu.src[0].chan = 3;
 
@@ -1555,7 +1554,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 			for (j = 0; j < 4; j++) {
 				struct r600_bytecode_alu alu;
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4);
+				alu.op = ALU_OP2_DOT4;
 				alu.src[0].sel = shader->output[ctx.cv_output].gpr;
 				alu.src[0].chan = j;
 
@@ -1611,7 +1610,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 				for (j = 0; j < so.output[i].num_components; j++) {
 					struct r600_bytecode_alu alu;
 					memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-					alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+					alu.op = ALU_OP1_MOV;
 					alu.src[0].sel = so_gpr[i];
 					alu.src[0].chan = so.output[i].start_component + j;
 
@@ -1647,31 +1646,31 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 			if (ctx.bc->chip_class >= EVERGREEN) {
 				switch (so.output[i].output_buffer) {
 				case 0:
-					output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0;
+					output.op = CF_OP_MEM_STREAM0_BUF0;
 					break;
 				case 1:
-					output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1;
+					output.op = CF_OP_MEM_STREAM0_BUF1;
 					break;
 				case 2:
-					output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2;
+					output.op = CF_OP_MEM_STREAM0_BUF2;
 					break;
 				case 3:
-					output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3;
+					output.op = CF_OP_MEM_STREAM0_BUF3;
 					break;
 				}
 			} else {
 				switch (so.output[i].output_buffer) {
 				case 0:
-					output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0;
+					output.op = CF_OP_MEM_STREAM0;
 					break;
 				case 1:
-					output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1;
+					output.op = CF_OP_MEM_STREAM1;
 					break;
 				case 2:
-					output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2;
+					output.op = CF_OP_MEM_STREAM2;
 					break;
 				case 3:
-					output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3;
+					output.op = CF_OP_MEM_STREAM3;
 					break;
 				}
 			}
@@ -1693,7 +1692,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 		output[j].burst_count = 1;
 		output[j].barrier = 1;
 		output[j].type = -1;
-		output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
+		output[j].op = CF_OP_EXPORT;
 		switch (ctx.type) {
 		case TGSI_PROCESSOR_VERTEX:
 			switch (shader->output[i].name) {
@@ -1754,7 +1753,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 						output[j].burst_count = 1;
 						output[j].barrier = 1;
 						output[j].array_base = next_pixel_base++;
-						output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
+						output[j].op = CF_OP_EXPORT;
 						output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 						shader->nr_ps_color_exports++;
 					}
@@ -1802,7 +1801,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 			output[j].barrier = 1;
 			output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
 			output[j].array_base = next_pos_base;
-			output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
+			output[j].op = CF_OP_EXPORT;
 			j++;
 	}
 
@@ -1819,7 +1818,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 			output[j].barrier = 1;
 			output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
 			output[j].array_base = 0;
-			output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
+			output[j].op = CF_OP_EXPORT;
 			j++;
 	}
 
@@ -1836,7 +1835,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 		output[j].barrier = 1;
 		output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 		output[j].array_base = 0;
-		output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
+		output[j].op = CF_OP_EXPORT;
 		j++;
 	}
 
@@ -1851,7 +1850,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
 		}
 		if (!(output_done & (1 << output[i].type))) {
 			output_done |= (1 << output[i].type);
-			output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
+			output[i].op = CF_OP_EXPORT_DONE;
 		}
 	}
 	/* add output to bytecode */
@@ -1963,7 +1962,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 		if (!swap) {
 			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 				r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
@@ -2020,7 +2019,7 @@ static int tgsi_ineg(struct r600_shader_ctx *ctx)
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
 			continue;
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 
 		alu.src[0].sel = V_SQ_ALU_SRC_0;
 
@@ -2048,7 +2047,7 @@ static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
 	
 	for (i = 0 ; i < last_slot; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 		for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 			r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
 
@@ -2081,7 +2080,7 @@ static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
 
 		for (i = 0 ; i < 4; i++) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = ctx->inst_info->r600_opcode;
+			alu.op = ctx->inst_info->op;
 			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 				r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
 			}
@@ -2112,7 +2111,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
 	struct r600_bytecode_alu alu;
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+	alu.op = ALU_OP3_MULADD;
 	alu.is_op3 = 1;
 
 	alu.dst.chan = 0;
@@ -2132,7 +2131,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
 		return r;
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
+	alu.op = ALU_OP1_FRACT;
 
 	alu.dst.chan = 0;
 	alu.dst.sel = ctx->temp_reg;
@@ -2146,7 +2145,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
 		return r;
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+	alu.op = ALU_OP3_MULADD;
 	alu.is_op3 = 1;
 
 	alu.dst.chan = 0;
@@ -2191,7 +2190,7 @@ static int cayman_trig(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < last_slot; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 		alu.dst.chan = i;
 
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -2220,7 +2219,7 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 		return r;
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = ctx->inst_info->r600_opcode;
+	alu.op = ctx->inst_info->op;
 	alu.dst.chan = 0;
 	alu.dst.sel = ctx->temp_reg;
 	alu.dst.write = 1;
@@ -2238,7 +2237,7 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 
 		alu.src[0].sel = ctx->temp_reg;
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -2271,7 +2270,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0 ; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
+				alu.op = ALU_OP1_COS;
 				tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
 				if (i == 0)
@@ -2288,7 +2287,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
+			alu.op = ALU_OP1_COS;
 			tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
 
 			alu.src[0].sel = ctx->temp_reg;
@@ -2305,7 +2304,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0 ; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
+				alu.op = ALU_OP1_SIN;
 				tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 				if (i == 1)
 					alu.dst.write = 1;
@@ -2321,7 +2320,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
+			alu.op = ALU_OP1_SIN;
 			tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
 
 			alu.src[0].sel = ctx->temp_reg;
@@ -2337,7 +2336,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 
 		tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
 
@@ -2355,7 +2354,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 
 		tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
 
@@ -2379,7 +2378,7 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 
 		alu.dst.chan = i;
 
@@ -2413,7 +2412,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 
 	/* tmp.x = max(src.y, 0.0) */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
+	alu.op = ALU_OP2_MAX;
 	r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
 	alu.src[1].sel  = V_SQ_ALU_SRC_0; /*0.0*/
 	alu.src[1].chan = 1;
@@ -2437,7 +2436,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 			for (i = 0; i < 3; i++) {
 				/* tmp.z = log(tmp.x) */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
+				alu.op = ALU_OP1_LOG_CLAMPED;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 0;
 				alu.dst.sel = ctx->temp_reg;
@@ -2455,7 +2454,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		} else {
 			/* tmp.z = log(tmp.x) */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
+			alu.op = ALU_OP1_LOG_CLAMPED;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 0;
 			alu.dst.sel = ctx->temp_reg;
@@ -2472,7 +2471,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 
 		/* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
+		alu.op = ALU_OP3_MUL_LIT;
 		alu.src[0].sel  = sel;
 		alu.src[0].chan = chan;
 		r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
@@ -2490,7 +2489,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 			for (i = 0; i < 3; i++) {
 				/* dst.z = exp(tmp.x) */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+				alu.op = ALU_OP1_EXP_IEEE;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 0;
 				tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -2506,7 +2505,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		} else {
 			/* dst.z = exp(tmp.x) */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+			alu.op = ALU_OP1_EXP_IEEE;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 0;
 			tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
@@ -2519,7 +2518,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 
 	/* dst.x, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+	alu.op = ALU_OP1_MOV;
 	alu.src[0].sel  = V_SQ_ALU_SRC_1; /*1.0*/
 	alu.src[0].chan = 0;
 	tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
@@ -2530,7 +2529,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 
 	/* dst.y = max(src.x, 0.0) */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
+	alu.op = ALU_OP2_MAX;
 	r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 	alu.src[1].sel  = V_SQ_ALU_SRC_0; /*0.0*/
 	alu.src[1].chan = 0;
@@ -2542,7 +2541,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 
 	/* dst.w, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+	alu.op = ALU_OP1_MOV;
 	alu.src[0].sel  = V_SQ_ALU_SRC_1;
 	alu.src[0].chan = 0;
 	tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
@@ -2567,7 +2566,7 @@ static int tgsi_rsq(struct r600_shader_ctx *ctx)
 	 * For state trackers other than OpenGL, we'll want to use
 	 * _RECIPSQRT_IEEE instead.
 	 */
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
+	alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
 
 	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
 		r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
@@ -2592,7 +2591,7 @@ static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 		alu.src[0].sel = ctx->temp_reg;
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 		alu.dst.chan = i;
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 		alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
@@ -2612,7 +2611,7 @@ static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
 	int i, r;
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = ctx->inst_info->r600_opcode;
+	alu.op = ctx->inst_info->op;
 	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
 		r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
 	}
@@ -2635,7 +2634,7 @@ static int cayman_pow(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < 3; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+		alu.op = ALU_OP1_LOG_IEEE;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = i;
@@ -2649,7 +2648,7 @@ static int cayman_pow(struct r600_shader_ctx *ctx)
 
 	/* b * LOG2(a) */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+	alu.op = ALU_OP2_MUL;
 	r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
 	alu.src[1].sel = ctx->temp_reg;
 	alu.dst.sel = ctx->temp_reg;
@@ -2662,7 +2661,7 @@ static int cayman_pow(struct r600_shader_ctx *ctx)
 	for (i = 0; i < last_slot; i++) {
 		/* POW(a,b) = EXP2(b * LOG2(a))*/
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+		alu.op = ALU_OP1_EXP_IEEE;
 		alu.src[0].sel = ctx->temp_reg;
 
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -2683,7 +2682,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx)
 
 	/* LOG2(a) */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+	alu.op = ALU_OP1_LOG_IEEE;
 	r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 	alu.dst.sel = ctx->temp_reg;
 	alu.dst.write = 1;
@@ -2693,7 +2692,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx)
 		return r;
 	/* b * LOG2(a) */
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+	alu.op = ALU_OP2_MUL;
 	r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
 	alu.src[1].sel = ctx->temp_reg;
 	alu.dst.sel = ctx->temp_reg;
@@ -2704,7 +2703,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx)
 		return r;
 	/* POW(a,b) = EXP2(b * LOG2(a))*/
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+	alu.op = ALU_OP1_EXP_IEEE;
 	alu.src[0].sel = ctx->temp_reg;
 	alu.dst.sel = ctx->temp_reg;
 	alu.dst.write = 1;
@@ -2779,7 +2778,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* tmp2.x = -src0 */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+			alu.op = ALU_OP2_SUB_INT;
 
 			alu.dst.sel = tmp2;
 			alu.dst.chan = 0;
@@ -2795,7 +2794,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* tmp2.y = -src1 */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+			alu.op = ALU_OP2_SUB_INT;
 
 			alu.dst.sel = tmp2;
 			alu.dst.chan = 1;
@@ -2814,7 +2813,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			if (!mod) {
 
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT);
+				alu.op = ALU_OP2_XOR_INT;
 
 				alu.dst.sel = tmp2;
 				alu.dst.chan = 2;
@@ -2830,7 +2829,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* tmp2.x = |src0| */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+			alu.op = ALU_OP3_CNDGE_INT;
 			alu.is_op3 = 1;
 
 			alu.dst.sel = tmp2;
@@ -2848,7 +2847,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* tmp2.y = |src1| */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+			alu.op = ALU_OP3_CNDGE_INT;
 			alu.is_op3 = 1;
 
 			alu.dst.sel = tmp2;
@@ -2870,7 +2869,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		if (ctx->bc->chip_class == CAYMAN) {
 			/* tmp3.x = u2f(src2) */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
+			alu.op = ALU_OP1_UINT_TO_FLT;
 
 			alu.dst.sel = tmp3;
 			alu.dst.chan = 0;
@@ -2890,7 +2889,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			/* tmp0.x = recip(tmp3.x) */
 			for (j = 0 ; j < 3; j++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+				alu.op = ALU_OP1_RECIP_IEEE;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = j;
@@ -2906,7 +2905,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			}
 
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+			alu.op = ALU_OP2_MUL;
 
 			alu.src[0].sel = tmp0;
 			alu.src[0].chan = 0;
@@ -2922,7 +2921,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 				return r;
 
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
+			alu.op = ALU_OP1_FLT_TO_UINT;
 		  
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 0;
@@ -2937,7 +2936,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT);
+			alu.op = ALU_OP1_RECIP_UINT;
 
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 0;
@@ -2959,7 +2958,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (j = 0 ; j < 4; j++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+				alu.op = ALU_OP2_MULLO_UINT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = j;
@@ -2980,7 +2979,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+			alu.op = ALU_OP2_MULLO_UINT;
 
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 2;
@@ -3002,7 +3001,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 3. tmp0.w = -tmp0.z */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+		alu.op = ALU_OP2_SUB_INT;
 
 		alu.dst.sel = tmp0;
 		alu.dst.chan = 3;
@@ -3020,7 +3019,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (j = 0 ; j < 4; j++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+				alu.op = ALU_OP2_MULHI_UINT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = j;
@@ -3041,7 +3040,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+			alu.op = ALU_OP2_MULHI_UINT;
 
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 1;
@@ -3064,7 +3063,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z)      = abs(lo(rcp*src)) */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
+		alu.op = ALU_OP3_CNDE_INT;
 		alu.is_op3 = 1;
 
 		alu.dst.sel = tmp0;
@@ -3086,7 +3085,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (j = 0 ; j < 4; j++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+				alu.op = ALU_OP2_MULHI_UINT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = j;
@@ -3104,7 +3103,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+			alu.op = ALU_OP2_MULHI_UINT;
 
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 3;
@@ -3123,7 +3122,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 7. tmp1.x = tmp0.x - tmp0.w */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+		alu.op = ALU_OP2_SUB_INT;
 
 		alu.dst.sel = tmp1;
 		alu.dst.chan = 0;
@@ -3140,7 +3139,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 8. tmp1.y = tmp0.x + tmp0.w */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
+		alu.op = ALU_OP2_ADD_INT;
 
 		alu.dst.sel = tmp1;
 		alu.dst.chan = 1;
@@ -3157,7 +3156,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
+		alu.op = ALU_OP3_CNDE_INT;
 		alu.is_op3 = 1;
 
 		alu.dst.sel = tmp0;
@@ -3179,7 +3178,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (j = 0 ; j < 4; j++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+				alu.op = ALU_OP2_MULHI_UINT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = j;
@@ -3201,7 +3200,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+			alu.op = ALU_OP2_MULHI_UINT;
 
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 2;
@@ -3226,7 +3225,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (j = 0 ; j < 4; j++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+				alu.op = ALU_OP2_MULLO_UINT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = j;
@@ -3248,7 +3247,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+			alu.op = ALU_OP2_MULLO_UINT;
 
 			alu.dst.sel = tmp0;
 			alu.dst.chan = 1;
@@ -3271,7 +3270,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 12. tmp0.w = src1 - tmp0.y       = r */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+		alu.op = ALU_OP2_SUB_INT;
 
 		alu.dst.sel = tmp0;
 		alu.dst.chan = 3;
@@ -3293,7 +3292,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 13. tmp1.x = tmp0.w >= src2		= r >= src2 */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
+		alu.op = ALU_OP2_SETGE_UINT;
 
 		alu.dst.sel = tmp1;
 		alu.dst.chan = 0;
@@ -3314,7 +3313,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 14. tmp1.y = src1 >= tmp0.y       = r >= 0 */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
+		alu.op = ALU_OP2_SETGE_UINT;
 
 		alu.dst.sel = tmp1;
 		alu.dst.chan = 1;
@@ -3338,7 +3337,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* 15. tmp1.z = tmp0.w - src2			= r - src2 */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+			alu.op = ALU_OP2_SUB_INT;
 
 			alu.dst.sel = tmp1;
 			alu.dst.chan = 2;
@@ -3360,7 +3359,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* 16. tmp1.w = tmp0.w + src2			= r + src2 */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
+			alu.op = ALU_OP2_ADD_INT;
 
 			alu.dst.sel = tmp1;
 			alu.dst.chan = 3;
@@ -3383,7 +3382,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* 15. tmp1.z = tmp0.z + 1       = q + 1       DIV */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
+			alu.op = ALU_OP2_ADD_INT;
 
 			alu.dst.sel = tmp1;
 			alu.dst.chan = 2;
@@ -3399,7 +3398,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 			/* 16. tmp1.w = tmp0.z - 1			= q - 1 */
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
+			alu.op = ALU_OP2_ADD_INT;
 
 			alu.dst.sel = tmp1;
 			alu.dst.chan = 3;
@@ -3417,7 +3416,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 17. tmp1.x = tmp1.x & tmp1.y */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
+		alu.op = ALU_OP2_AND_INT;
 
 		alu.dst.sel = tmp1;
 		alu.dst.chan = 0;
@@ -3435,7 +3434,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 		/* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z    DIV */
 		/* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z    MOD */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
+		alu.op = ALU_OP3_CNDE_INT;
 		alu.is_op3 = 1;
 
 		alu.dst.sel = tmp0;
@@ -3455,7 +3454,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 		/* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
+		alu.op = ALU_OP3_CNDE_INT;
 		alu.is_op3 = 1;
 
 		if (signed_op) {
@@ -3485,7 +3484,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 				/* tmp0.x = -tmp0.z */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+				alu.op = ALU_OP2_SUB_INT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = 0;
@@ -3502,7 +3501,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 				/* sign of the remainder is the same as the sign of src0 */
 				/* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+				alu.op = ALU_OP3_CNDGE_INT;
 				alu.is_op3 = 1;
 
 				tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -3521,7 +3520,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 
 				/* tmp0.x = -tmp0.z */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+				alu.op = ALU_OP2_SUB_INT;
 
 				alu.dst.sel = tmp0;
 				alu.dst.chan = 0;
@@ -3538,7 +3537,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
 				/* fix the quotient sign (same as the sign of src0*src1) */
 				/* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+				alu.op = ALU_OP3_CNDGE_INT;
 				alu.is_op3 = 1;
 
 				tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -3593,7 +3592,7 @@ static int tgsi_f2i(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
+		alu.op = ALU_OP1_TRUNC;
 
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = i;
@@ -3612,14 +3611,14 @@ static int tgsi_f2i(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].chan = i;
 
-		if (i == last_inst || alu.inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT)
+		if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
 			alu.last = 1;
 		r = r600_bytecode_add_alu(ctx->bc, &alu);
 		if (r)
@@ -3643,7 +3642,7 @@ static int tgsi_iabs(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
+		alu.op = ALU_OP2_SUB_INT;
 
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = i;
@@ -3665,7 +3664,7 @@ static int tgsi_iabs(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+		alu.op = ALU_OP3_CNDGE_INT;
 		alu.is_op3 = 1;
 		alu.dst.write = 1;
 
@@ -3699,7 +3698,7 @@ static int tgsi_issg(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+		alu.op = ALU_OP3_CNDGE_INT;
 		alu.is_op3 = 1;
 
 		alu.dst.sel = ctx->temp_reg;
@@ -3723,7 +3722,7 @@ static int tgsi_issg(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT);
+		alu.op = ALU_OP3_CNDGT_INT;
 		alu.is_op3 = 1;
 		alu.dst.write = 1;
 
@@ -3757,7 +3756,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 	/* tmp = (src > 0 ? 1 : src) */
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
+		alu.op = ALU_OP3_CNDGT;
 		alu.is_op3 = 1;
 
 		alu.dst.sel = ctx->temp_reg;
@@ -3777,7 +3776,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 	/* dst = (-tmp > 0 ? -1 : tmp) */
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
+		alu.op = ALU_OP3_CNDGT;
 		alu.is_op3 = 1;
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
@@ -3808,10 +3807,10 @@ static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instru
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
+			alu.op = ALU_OP0_NOP;
 			alu.dst.chan = i;
 		} else {
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+			alu.op = ALU_OP1_MOV;
 			tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = i;
@@ -3838,7 +3837,7 @@ static int tgsi_op3(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 		for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 			r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
 		}
@@ -3865,7 +3864,7 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = ctx->inst_info->r600_opcode;
+		alu.op = ctx->inst_info->op;
 		for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 			r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
 		}
@@ -3936,7 +3935,7 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
 	if (src_requires_loading) {
 		for (i = 0; i < 4; i++) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+			alu.op = ALU_OP1_MOV;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = i;
@@ -3951,7 +3950,7 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
 	}
 
 	memset(&vtx, 0, sizeof(vtx));
-	vtx.inst = 0;
+	vtx.op = FETCH_OP_VFETCH;
 	vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
 	vtx.fetch_type = 2;		/* VTX_FETCH_NO_INDEX_OFFSET */
 	vtx.src_gpr = src_gpr;
@@ -3976,7 +3975,7 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
+		alu.op = ALU_OP2_AND_INT;
 
 		alu.dst.chan = i;
 		alu.dst.sel = vtx.dst_gpr;
@@ -3998,7 +3997,7 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
 
 	if (inst->Dst[0].Register.WriteMask & 3) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT);
+		alu.op = ALU_OP2_OR_INT;
 
 		alu.dst.chan = 3;
 		alu.dst.sel = vtx.dst_gpr;
@@ -4027,7 +4026,7 @@ static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
 	int id = tgsi_tex_get_src_gpr(ctx, 1);
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+	alu.op = ALU_OP1_MOV;
 
 	if (ctx->bc->chip_class >= EVERGREEN) {
 		alu.src[0].sel = 512 + (id / 4);
@@ -4112,8 +4111,8 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		for (i = 1; i < 3; i++) {
 			/* set gradients h/v */
 			memset(&tex, 0, sizeof(struct r600_bytecode_tex));
-			tex.inst = (i == 1) ? SQ_TEX_INST_SET_GRADIENTS_H :
-				SQ_TEX_INST_SET_GRADIENTS_V;
+			tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
+				FETCH_OP_SET_GRADIENTS_V;
 			tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
 			tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
 
@@ -4126,7 +4125,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 				for (j = 0; j < 4; j++) {
 					memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-					alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+					alu.op = ALU_OP1_MOV;
                                         r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
                                         alu.dst.sel = tex.src_gpr;
                                         alu.dst.chan = j;
@@ -4165,7 +4164,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 			out_chan = 2;
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+				alu.op = ALU_OP1_RECIP_IEEE;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
 
 				alu.dst.sel = ctx->temp_reg;
@@ -4182,7 +4181,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		} else {
 			out_chan = 3;
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+			alu.op = ALU_OP1_RECIP_IEEE;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
 
 			alu.dst.sel = ctx->temp_reg;
@@ -4196,7 +4195,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 		for (i = 0; i < 3; i++) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+			alu.op = ALU_OP2_MUL;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = out_chan;
 			r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
@@ -4208,7 +4207,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 				return r;
 		}
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		alu.dst.sel = ctx->temp_reg;
@@ -4235,7 +4234,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		/* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
 		for (i = 0; i < 4; i++) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
+			alu.op = ALU_OP2_CUBE;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
 			r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
 			alu.dst.sel = ctx->temp_reg;
@@ -4252,7 +4251,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+				alu.op = ALU_OP1_RECIP_IEEE;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 2;
 				alu.src[0].abs = 1;
@@ -4268,7 +4267,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+			alu.op = ALU_OP1_RECIP_IEEE;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 2;
 			alu.src[0].abs = 1;
@@ -4286,7 +4285,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		 * muladd has no writemask, have to use another temp
 		 */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+		alu.op = ALU_OP3_MULADD;
 		alu.is_op3 = 1;
 
 		alu.src[0].sel = ctx->temp_reg;
@@ -4307,7 +4306,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 			return r;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+		alu.op = ALU_OP3_MULADD;
 		alu.is_op3 = 1;
 
 		alu.src[0].sel = ctx->temp_reg;
@@ -4333,7 +4332,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
 		    inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+			alu.op = ALU_OP1_MOV;
 			if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
 				r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
 			else
@@ -4353,7 +4352,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 				int mytmp = r600_get_temp(ctx);
 				static const float eight = 8.0f;
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+				alu.op = ALU_OP1_MOV;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 3;
 				alu.dst.sel = mytmp;
@@ -4366,7 +4365,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 				/* have to multiply original layer by 8 and add to face id (temp.w) in Z */
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+				alu.op = ALU_OP3_MULADD;
 				alu.is_op3 = 1;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
 				alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -4383,7 +4382,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 					return r;
 			} else if (ctx->bc->chip_class < EVERGREEN) {
 				memset(&tex, 0, sizeof(struct r600_bytecode_tex));
-				tex.inst = SQ_TEX_INST_SET_CUBEMAP_INDEX;
+				tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
 				tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
 				tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
 				tex.src_gpr = r600_get_temp(ctx);
@@ -4397,7 +4396,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 				tex.coord_type_z = 1;
 				tex.coord_type_w = 1;
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+				alu.op = ALU_OP1_MOV;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
 				alu.dst.sel = tex.src_gpr;
 				alu.dst.chan = 0;
@@ -4420,7 +4419,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		    inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
 		    inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+			alu.op = ALU_OP1_MOV;
 			if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
 			    inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
 				r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
@@ -4442,7 +4441,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	if (src_requires_loading && !src_loaded) {
 		for (i = 0; i < 4; i++) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+			alu.op = ALU_OP1_MOV;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = i;
@@ -4475,7 +4474,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 		/* temp.w = ldfptr() */
 		memset(&tex, 0, sizeof(struct r600_bytecode_tex));
-		tex.inst = SQ_TEX_INST_LD;
+		tex.op = FETCH_OP_LD;
 		tex.inst_mod = 1; /* to indicate this is ldfptr */
 		tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
 		tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
@@ -4500,7 +4499,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0 ; i < 4; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = ctx->inst_info->r600_opcode;
+				alu.op = ctx->inst_info->op;
 				alu.src[0].sel = src_gpr;
 				alu.src[0].chan = sample_chan;
 				alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -4516,7 +4515,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT);
+			alu.op = ALU_OP2_MULLO_INT;
 			alu.src[0].sel = src_gpr;
 			alu.src[0].chan = sample_chan;
 			alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -4532,7 +4531,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 		/* sample_index = temp.w >> temp.x */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT);
+		alu.op = ALU_OP2_LSHR_INT;
 		alu.src[0].sel = temp;
 		alu.src[0].chan = 3;
 		alu.src[1].sel = temp;
@@ -4547,7 +4546,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 		/* sample_index & 0xF */
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
+		alu.op = ALU_OP2_AND_INT;
 		alu.src[0].sel = src_gpr;
 		alu.src[0].chan = sample_chan;
 		alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
@@ -4563,7 +4562,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		/* visualize the FMASK */
 		for (i = 0; i < 4; i++) {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
+			alu.op = ALU_OP1_INT_TO_FLT;
 			alu.src[0].sel = src_gpr;
 			alu.src[0].chan = sample_chan;
 			alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
@@ -4583,7 +4582,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
 		
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 
 		alu.src[0].sel = 512 + (id / 4);
 		alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
@@ -4597,7 +4596,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		inst->Dst[0].Register.WriteMask &= ~4;
 	}
 
-	opcode = ctx->inst_info->r600_opcode;
+	opcode = ctx->inst_info->op;
 	if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
 	    inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
 	    inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
@@ -4606,23 +4605,23 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	    inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
 	    inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
 		switch (opcode) {
-		case SQ_TEX_INST_SAMPLE:
-			opcode = SQ_TEX_INST_SAMPLE_C;
+		case FETCH_OP_SAMPLE:
+			opcode = FETCH_OP_SAMPLE_C;
 			break;
-		case SQ_TEX_INST_SAMPLE_L:
-			opcode = SQ_TEX_INST_SAMPLE_C_L;
+		case FETCH_OP_SAMPLE_L:
+			opcode = FETCH_OP_SAMPLE_C_L;
 			break;
-		case SQ_TEX_INST_SAMPLE_LB:
-			opcode = SQ_TEX_INST_SAMPLE_C_LB;
+		case FETCH_OP_SAMPLE_LB:
+			opcode = FETCH_OP_SAMPLE_C_LB;
 			break;
-		case SQ_TEX_INST_SAMPLE_G:
-			opcode = SQ_TEX_INST_SAMPLE_C_G;
+		case FETCH_OP_SAMPLE_G:
+			opcode = FETCH_OP_SAMPLE_C_G;
 			break;
 		}
 	}
 
 	memset(&tex, 0, sizeof(struct r600_bytecode_tex));
-	tex.inst = opcode;
+	tex.op = opcode;
 
 	tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
 	tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
@@ -4680,15 +4679,15 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	     inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
 	     inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
 	     inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
-	    opcode != SQ_TEX_INST_SAMPLE_C_L &&
-	    opcode != SQ_TEX_INST_SAMPLE_C_LB) {
+	    opcode != FETCH_OP_SAMPLE_C_L &&
+	    opcode != FETCH_OP_SAMPLE_C_LB) {
 		tex.src_sel_w = tex.src_sel_z;
 	}
 
 	if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
 	    inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
-		if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
-		    opcode == SQ_TEX_INST_SAMPLE_C_LB) {
+		if (opcode == FETCH_OP_SAMPLE_C_L ||
+		    opcode == FETCH_OP_SAMPLE_C_LB) {
 			/* the array index is read from Y */
 			tex.coord_type_y = 0;
 		} else {
@@ -4727,7 +4726,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 				continue;
 
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
+			alu.op = ALU_OP2_ADD;
 			r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
 			r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
 			alu.omod = 3;
@@ -4749,7 +4748,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
+		alu.op = ALU_OP2_ADD;
 		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
@@ -4771,7 +4770,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+		alu.op = ALU_OP2_MUL;
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].chan = i;
 		r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
@@ -4792,7 +4791,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+		alu.op = ALU_OP3_MULADD;
 		alu.is_op3 = 1;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
 		r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
@@ -4823,7 +4822,7 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
+		alu.op = ALU_OP3_CNDGE;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
 		r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
 		r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
@@ -4852,7 +4851,7 @@ static int tgsi_ucmp(struct r600_shader_ctx *ctx)
 			continue;
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
+		alu.op = ALU_OP3_CNDGE_INT;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
 		r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
 		r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
@@ -4883,7 +4882,7 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+		alu.op = ALU_OP2_MUL;
 		if (i < 3) {
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
 			r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
@@ -4907,7 +4906,7 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
+		alu.op = ALU_OP3_MULADD;
 
 		if (i < 3) {
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
@@ -4952,7 +4951,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 	if (inst->Dst[0].Register.WriteMask & 1) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
+		alu.op = ALU_OP1_FLOOR;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 
 		alu.dst.sel = ctx->temp_reg;
@@ -4965,7 +4964,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+				alu.op = ALU_OP1_EXP_IEEE;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 0;
 
@@ -4978,7 +4977,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 					return r;
 			}
 		} else {
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+			alu.op = ALU_OP1_EXP_IEEE;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 0;
 
@@ -4996,7 +4995,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 	if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
+		alu.op = ALU_OP1_FRACT;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 
 		alu.dst.sel = ctx->temp_reg;
@@ -5020,7 +5019,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+				alu.op = ALU_OP1_EXP_IEEE;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 
 				alu.dst.sel = ctx->temp_reg;
@@ -5036,7 +5035,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+			alu.op = ALU_OP1_EXP_IEEE;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 
 			alu.dst.sel = ctx->temp_reg;
@@ -5055,7 +5054,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 	if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 
@@ -5083,7 +5082,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+				alu.op = ALU_OP1_LOG_IEEE;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 				r600_bytecode_src_set_abs(&alu.src[0]);
 			
@@ -5101,7 +5100,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+			alu.op = ALU_OP1_LOG_IEEE;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 			r600_bytecode_src_set_abs(&alu.src[0]);
 			
@@ -5114,7 +5113,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 				return r;
 		}
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
+		alu.op = ALU_OP1_FLOOR;
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].chan = 0;
 
@@ -5135,7 +5134,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+				alu.op = ALU_OP1_LOG_IEEE;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 				r600_bytecode_src_set_abs(&alu.src[0]);
 
@@ -5153,7 +5152,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+			alu.op = ALU_OP1_LOG_IEEE;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 			r600_bytecode_src_set_abs(&alu.src[0]);
 
@@ -5169,7 +5168,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
+		alu.op = ALU_OP1_FLOOR;
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].chan = 1;
 
@@ -5185,7 +5184,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+				alu.op = ALU_OP1_EXP_IEEE;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 1;
 
@@ -5202,7 +5201,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
+			alu.op = ALU_OP1_EXP_IEEE;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 1;
 
@@ -5219,7 +5218,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+				alu.op = ALU_OP1_RECIP_IEEE;
 				alu.src[0].sel = ctx->temp_reg;
 				alu.src[0].chan = 1;
 
@@ -5236,7 +5235,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			}
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+			alu.op = ALU_OP1_RECIP_IEEE;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 1;
 
@@ -5252,7 +5251,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+		alu.op = ALU_OP2_MUL;
 
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 		r600_bytecode_src_set_abs(&alu.src[0]);
@@ -5276,7 +5275,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+				alu.op = ALU_OP1_LOG_IEEE;
 				r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 				r600_bytecode_src_set_abs(&alu.src[0]);
 
@@ -5294,7 +5293,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		} else {
 			memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
+			alu.op = ALU_OP1_LOG_IEEE;
 			r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 			r600_bytecode_src_set_abs(&alu.src[0]);
 
@@ -5313,7 +5312,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 	if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+		alu.op = ALU_OP1_MOV;
 		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 
@@ -5340,13 +5339,13 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
 
 	switch (inst->Instruction.Opcode) {
 	case TGSI_OPCODE_ARL:
-		alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
+		alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
 		break;
 	case TGSI_OPCODE_ARR:
-		alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
+		alu.op = ALU_OP1_FLT_TO_INT;
 		break;
 	case TGSI_OPCODE_UARL:
-		alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.op = ALU_OP1_MOV;
 		break;
 	default:
 		assert(0);
@@ -5373,7 +5372,7 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
 	switch (inst->Instruction.Opcode) {
 	case TGSI_OPCODE_ARL:
 		memset(&alu, 0, sizeof(alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
+		alu.op = ALU_OP1_FLOOR;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 		alu.dst.sel = ctx->bc->ar_reg;
 		alu.dst.write = 1;
@@ -5383,7 +5382,7 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
 			return r;
 
 		memset(&alu, 0, sizeof(alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
+		alu.op = ALU_OP1_FLT_TO_INT;
 		alu.src[0].sel = ctx->bc->ar_reg;
 		alu.dst.sel = ctx->bc->ar_reg;
 		alu.dst.write = 1;
@@ -5394,7 +5393,7 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
 		break;
 	case TGSI_OPCODE_ARR:
 		memset(&alu, 0, sizeof(alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
+		alu.op = ALU_OP1_FLT_TO_INT;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 		alu.dst.sel = ctx->bc->ar_reg;
 		alu.dst.write = 1;
@@ -5405,7 +5404,7 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
 		break;
 	case TGSI_OPCODE_UARL:
 		memset(&alu, 0, sizeof(alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.op = ALU_OP1_MOV;
 		r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
 		alu.dst.sel = ctx->bc->ar_reg;
 		alu.dst.write = 1;
@@ -5432,7 +5431,7 @@ static int tgsi_opdst(struct r600_shader_ctx *ctx)
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
+		alu.op = ALU_OP2_MUL;
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
 		if (i == 0 || i == 3) {
@@ -5461,7 +5460,7 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 	int r;
 
 	memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-	alu.inst = opcode;
+	alu.op = opcode;
 	alu.execute_mask = 1;
 	alu.update_pred = 1;
 
@@ -5475,7 +5474,7 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 
 	alu.last = 1;
 
-	r = r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
+	r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
 	if (r)
 		return r;
 	return 0;
@@ -5488,17 +5487,17 @@ static int pops(struct r600_shader_ctx *ctx, int pops)
 	if (!force_pop) {
 		int alu_pop = 3;
 		if (ctx->bc->cf_last) {
-			if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU))
+			if (ctx->bc->cf_last->op == CF_OP_ALU)
 				alu_pop = 0;
-			else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER))
+			else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
 				alu_pop = 1;
 		}
 		alu_pop += pops;
 		if (alu_pop == 1) {
-			ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER);
+			ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
 			ctx->bc->force_add_cf = 1;
 		} else if (alu_pop == 2) {
-			ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER);
+			ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
 			ctx->bc->force_add_cf = 1;
 		} else {
 			force_pop = 1;
@@ -5506,7 +5505,7 @@ static int pops(struct r600_shader_ctx *ctx, int pops)
 	}
 
 	if (force_pop) {
-		r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
+		r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
 		ctx->bc->cf_last->pop_count = pops;
 		ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
 	}
@@ -5604,14 +5603,14 @@ static void fc_poplevel(struct r600_shader_ctx *ctx)
 #if 0
 static int emit_return(struct r600_shader_ctx *ctx)
 {
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
 	return 0;
 }
 
 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
 {
 
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
 	ctx->bc->cf_last->pop_count = pops;
 	/* XXX work out offset */
 	return 0;
@@ -5640,7 +5639,7 @@ static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
 {
 	emit_testflag(ctx);
 
-	r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
+	r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
 	ctx->bc->cf_last->pop_count = 1;
 
 	fc_set_mid(ctx, fc_sp);
@@ -5651,9 +5650,9 @@ static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
 
 static int tgsi_if(struct r600_shader_ctx *ctx)
 {
-	emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
+	emit_logic_pred(ctx, ALU_OP2_PRED_SETNE_INT);
 
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
 
 	fc_pushlevel(ctx, FC_IF);
 
@@ -5663,7 +5662,7 @@ static int tgsi_if(struct r600_shader_ctx *ctx)
 
 static int tgsi_else(struct r600_shader_ctx *ctx)
 {
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
 	ctx->bc->cf_last->pop_count = 1;
 
 	fc_set_mid(ctx, ctx->bc->fc_sp);
@@ -5695,7 +5694,7 @@ static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
 {
 	/* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
 	 * limited to 4096 iterations, like the other LOOP_* instructions. */
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
 
 	fc_pushlevel(ctx, FC_LOOP);
 
@@ -5708,7 +5707,7 @@ static int tgsi_endloop(struct r600_shader_ctx *ctx)
 {
 	int i;
 
-	r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
+	r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
 
 	if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
 		R600_ERR("loop/endloop in shader code are not paired.\n");
@@ -5748,7 +5747,7 @@ static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
 		return -EINVAL;
 	}
 
-	r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
+	r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
 
 	fc_set_mid(ctx, fscp);
 
@@ -5774,7 +5773,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.write = 1;
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+		alu.op = ALU_OP2_MULLO_UINT;
 		for (j = 0; j < 2; j++) {
 		        r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
 		}
@@ -5793,7 +5792,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
 		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
+		alu.op = ALU_OP2_ADD_INT;
 
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].chan = i;
@@ -5810,166 +5809,166 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
 }
 
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
-	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
-	{TGSI_OPCODE_MOV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-	{TGSI_OPCODE_LIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
+	{TGSI_OPCODE_ARL,	0, ALU_OP0_NOP, tgsi_r600_arl},
+	{TGSI_OPCODE_MOV,	0, ALU_OP1_MOV, tgsi_op2},
+	{TGSI_OPCODE_LIT,	0, ALU_OP0_NOP, tgsi_lit},
 
 	/* XXX:
 	 * For state trackers other than OpenGL, we'll want to use
 	 * _RECIP_IEEE instead.
 	 */
-	{TGSI_OPCODE_RCP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
-
-	{TGSI_OPCODE_RSQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
-	{TGSI_OPCODE_EXP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
-	{TGSI_OPCODE_LOG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
-	{TGSI_OPCODE_MUL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
-	{TGSI_OPCODE_ADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_DP3,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DP4,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
-	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
-	{TGSI_OPCODE_MAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
-	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
-	{TGSI_OPCODE_SGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
-	{TGSI_OPCODE_MAD,	1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
-	{TGSI_OPCODE_SUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_LRP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
-	{TGSI_OPCODE_CND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RCP,	0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
+
+	{TGSI_OPCODE_RSQ,	0, ALU_OP0_NOP, tgsi_rsq},
+	{TGSI_OPCODE_EXP,	0, ALU_OP0_NOP, tgsi_exp},
+	{TGSI_OPCODE_LOG,	0, ALU_OP0_NOP, tgsi_log},
+	{TGSI_OPCODE_MUL,	0, ALU_OP2_MUL, tgsi_op2},
+	{TGSI_OPCODE_ADD,	0, ALU_OP2_ADD, tgsi_op2},
+	{TGSI_OPCODE_DP3,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DP4,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DST,	0, ALU_OP0_NOP, tgsi_opdst},
+	{TGSI_OPCODE_MIN,	0, ALU_OP2_MIN, tgsi_op2},
+	{TGSI_OPCODE_MAX,	0, ALU_OP2_MAX, tgsi_op2},
+	{TGSI_OPCODE_SLT,	0, ALU_OP2_SETGT, tgsi_op2_swap},
+	{TGSI_OPCODE_SGE,	0, ALU_OP2_SETGE, tgsi_op2},
+	{TGSI_OPCODE_MAD,	1, ALU_OP3_MULADD, tgsi_op3},
+	{TGSI_OPCODE_SUB,	0, ALU_OP2_ADD, tgsi_op2},
+	{TGSI_OPCODE_LRP,	0, ALU_OP0_NOP, tgsi_lrp},
+	{TGSI_OPCODE_CND,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{20,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DP2A,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{20,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2A,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{22,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{23,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FRC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
-	{TGSI_OPCODE_CLAMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
-	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
-	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
-	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
+	{22,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{23,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FRC,	0, ALU_OP1_FRACT, tgsi_op2},
+	{TGSI_OPCODE_CLAMP,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FLR,	0, ALU_OP1_FLOOR, tgsi_op2},
+	{TGSI_OPCODE_ROUND,	0, ALU_OP1_RNDNE, tgsi_op2},
+	{TGSI_OPCODE_EX2,	0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_LG2,	0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_POW,	0, ALU_OP0_NOP, tgsi_pow},
+	{TGSI_OPCODE_XPD,	0, ALU_OP0_NOP, tgsi_xpd},
 	/* gap */
-	{32,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-	{TGSI_OPCODE_RCC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
-	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
-	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
-	{TGSI_OPCODE_KILP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* predicated kill */
-	{TGSI_OPCODE_PK2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK2US,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK4B,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK4UB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SEQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
-	{TGSI_OPCODE_SFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SGT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
-	{TGSI_OPCODE_SIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
-	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
-	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
-	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_TXD,	0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
-	{TGSI_OPCODE_TXP,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_UP2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP2US,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP4B,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP4UB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_X2D,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ARA,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ARR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
-	{TGSI_OPCODE_BRA,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CAL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RET,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SSG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
-	{TGSI_OPCODE_CMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
-	{TGSI_OPCODE_SCS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
-	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
-	{TGSI_OPCODE_NRM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DP2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_TXL,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
-	{TGSI_OPCODE_BRK,	0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
-	{TGSI_OPCODE_IF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
+	{32,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ABS,	0, ALU_OP1_MOV, tgsi_op2},
+	{TGSI_OPCODE_RCC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DPH,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_COS,	0, ALU_OP1_COS, tgsi_trig},
+	{TGSI_OPCODE_DDX,	0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
+	{TGSI_OPCODE_DDY,	0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
+	{TGSI_OPCODE_KILP,	0, ALU_OP2_KILLGT, tgsi_kill},  /* predicated kill */
+	{TGSI_OPCODE_PK2H,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK2US,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4B,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4UB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RFL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SEQ,	0, ALU_OP2_SETE, tgsi_op2},
+	{TGSI_OPCODE_SFL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SGT,	0, ALU_OP2_SETGT, tgsi_op2},
+	{TGSI_OPCODE_SIN,	0, ALU_OP1_SIN, tgsi_trig},
+	{TGSI_OPCODE_SLE,	0, ALU_OP2_SETGE, tgsi_op2_swap},
+	{TGSI_OPCODE_SNE,	0, ALU_OP2_SETNE, tgsi_op2},
+	{TGSI_OPCODE_STR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXD,	0, FETCH_OP_SAMPLE_G, tgsi_tex},
+	{TGSI_OPCODE_TXP,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_UP2H,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP2US,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4B,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4UB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_X2D,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARR,	0, ALU_OP0_NOP, tgsi_r600_arl},
+	{TGSI_OPCODE_BRA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CAL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RET,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SSG,	0, ALU_OP0_NOP, tgsi_ssg},
+	{TGSI_OPCODE_CMP,	0, ALU_OP0_NOP, tgsi_cmp},
+	{TGSI_OPCODE_SCS,	0, ALU_OP0_NOP, tgsi_scs},
+	{TGSI_OPCODE_TXB,	0, FETCH_OP_SAMPLE_LB, tgsi_tex},
+	{TGSI_OPCODE_NRM,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DIV,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_TXL,	0, FETCH_OP_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_BRK,	0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_IF,	0, ALU_OP0_NOP, tgsi_if},
 	/* gap */
-	{75,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{76,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ELSE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
-	{TGSI_OPCODE_ENDIF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
+	{75,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{76,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ELSE,	0, ALU_OP0_NOP, tgsi_else},
+	{TGSI_OPCODE_ENDIF,	0, ALU_OP0_NOP, tgsi_endif},
 	/* gap */
-	{79,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{80,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PUSHA,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_POPA,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CEIL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
-	{TGSI_OPCODE_I2F,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
-	{TGSI_OPCODE_NOT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
-	{TGSI_OPCODE_TRUNC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
-	{TGSI_OPCODE_SHL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2_trans},
+	{79,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{80,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PUSHA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_POPA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CEIL,	0, ALU_OP1_CEIL, tgsi_op2},
+	{TGSI_OPCODE_I2F,	0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
+	{TGSI_OPCODE_NOT,	0, ALU_OP1_NOT_INT, tgsi_op2},
+	{TGSI_OPCODE_TRUNC,	0, ALU_OP1_TRUNC, tgsi_op2},
+	{TGSI_OPCODE_SHL,	0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
 	/* gap */
-	{88,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_AND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
-	{TGSI_OPCODE_OR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
-	{TGSI_OPCODE_MOD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
-	{TGSI_OPCODE_XOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
-	{TGSI_OPCODE_SAD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXF,	0, SQ_TEX_INST_LD, tgsi_tex},
-	{TGSI_OPCODE_TXQ,	0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
-	{TGSI_OPCODE_CONT,	0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
-	{TGSI_OPCODE_EMIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDPRIM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BGNLOOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
-	{TGSI_OPCODE_BGNSUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDLOOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
-	{TGSI_OPCODE_ENDSUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXQ_LZ,	0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
+	{88,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_AND,	0, ALU_OP2_AND_INT, tgsi_op2},
+	{TGSI_OPCODE_OR,	0, ALU_OP2_OR_INT, tgsi_op2},
+	{TGSI_OPCODE_MOD,	0, ALU_OP0_NOP, tgsi_imod},
+	{TGSI_OPCODE_XOR,	0, ALU_OP2_XOR_INT, tgsi_op2},
+	{TGSI_OPCODE_SAD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXF,	0, FETCH_OP_LD, tgsi_tex},
+	{TGSI_OPCODE_TXQ,	0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
+	{TGSI_OPCODE_CONT,	0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_EMIT,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDPRIM,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BGNLOOP,	0, ALU_OP0_NOP, tgsi_bgnloop},
+	{TGSI_OPCODE_BGNSUB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDLOOP,	0, ALU_OP0_NOP, tgsi_endloop},
+	{TGSI_OPCODE_ENDSUB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXQ_LZ,	0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
 	/* gap */
-	{104,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{105,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{106,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_NOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{104,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{105,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{106,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NOP,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{108,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{109,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{110,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{111,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_NRM4,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CALLNZ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_IFC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BREAKC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_KIL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* conditional kill */
-	{TGSI_OPCODE_END,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
+	{108,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{109,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{110,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{111,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NRM4,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CALLNZ,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IFC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BREAKC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_KIL,	0, ALU_OP2_KILLGT, tgsi_kill},  /* conditional kill */
+	{TGSI_OPCODE_END,	0, ALU_OP0_NOP, tgsi_end},  /* aka HALT */
 	/* gap */
-	{118,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_F2I,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2_trans},
-	{TGSI_OPCODE_IDIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
-	{TGSI_OPCODE_IMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
-	{TGSI_OPCODE_IMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
-	{TGSI_OPCODE_INEG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
-	{TGSI_OPCODE_ISGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
-	{TGSI_OPCODE_ISHR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2_trans},
-	{TGSI_OPCODE_ISLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
-	{TGSI_OPCODE_F2U,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2_trans},
-	{TGSI_OPCODE_U2F,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
-	{TGSI_OPCODE_UADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
-	{TGSI_OPCODE_UDIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
-	{TGSI_OPCODE_UMAD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
-	{TGSI_OPCODE_UMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
-	{TGSI_OPCODE_UMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
-	{TGSI_OPCODE_UMOD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
-	{TGSI_OPCODE_UMUL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
-	{TGSI_OPCODE_USEQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
-	{TGSI_OPCODE_USGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
-	{TGSI_OPCODE_USHR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2_trans},
-	{TGSI_OPCODE_USLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
-	{TGSI_OPCODE_USNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
-	{TGSI_OPCODE_SWITCH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CASE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DEFAULT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDSWITCH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{118,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_F2I,	0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
+	{TGSI_OPCODE_IDIV,	0, ALU_OP0_NOP, tgsi_idiv},
+	{TGSI_OPCODE_IMAX,	0, ALU_OP2_MAX_INT, tgsi_op2},
+	{TGSI_OPCODE_IMIN,	0, ALU_OP2_MIN_INT, tgsi_op2},
+	{TGSI_OPCODE_INEG,	0, ALU_OP2_SUB_INT, tgsi_ineg},
+	{TGSI_OPCODE_ISGE,	0, ALU_OP2_SETGE_INT, tgsi_op2},
+	{TGSI_OPCODE_ISHR,	0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
+	{TGSI_OPCODE_ISLT,	0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
+	{TGSI_OPCODE_F2U,	0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
+	{TGSI_OPCODE_U2F,	0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
+	{TGSI_OPCODE_UADD,	0, ALU_OP2_ADD_INT, tgsi_op2},
+	{TGSI_OPCODE_UDIV,	0, ALU_OP0_NOP, tgsi_udiv},
+	{TGSI_OPCODE_UMAD,	0, ALU_OP0_NOP, tgsi_umad},
+	{TGSI_OPCODE_UMAX,	0, ALU_OP2_MAX_UINT, tgsi_op2},
+	{TGSI_OPCODE_UMIN,	0, ALU_OP2_MIN_UINT, tgsi_op2},
+	{TGSI_OPCODE_UMOD,	0, ALU_OP0_NOP, tgsi_umod},
+	{TGSI_OPCODE_UMUL,	0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
+	{TGSI_OPCODE_USEQ,	0, ALU_OP2_SETE_INT, tgsi_op2},
+	{TGSI_OPCODE_USGE,	0, ALU_OP2_SETGE_UINT, tgsi_op2},
+	{TGSI_OPCODE_USHR,	0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
+	{TGSI_OPCODE_USLT,	0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
+	{TGSI_OPCODE_USNE,	0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
+	{TGSI_OPCODE_SWITCH,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CASE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DEFAULT,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDSWITCH,	0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE,    0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_I,  0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
@@ -5982,187 +5981,187 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SVIEWINFO,	0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
-	{TGSI_OPCODE_UARL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
-	{TGSI_OPCODE_UCMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ucmp},
+	{TGSI_OPCODE_UARL,      0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
+	{TGSI_OPCODE_UCMP,	0, ALU_OP0_NOP, tgsi_ucmp},
 	{TGSI_OPCODE_IABS,      0, 0, tgsi_iabs},
 	{TGSI_OPCODE_ISSG,      0, 0, tgsi_issg},
-	{TGSI_OPCODE_LOAD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_STORE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_MFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_LFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BARRIER,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMXCHG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMCAS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMAND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMXOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMIMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMIMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX2,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_TXB2,	0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
-	{TGSI_OPCODE_TXL2,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
-	{TGSI_OPCODE_LAST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LOAD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_STORE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BARRIER,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUADD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMXCHG,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMCAS,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMAND,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMOR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMXOR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUMIN,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUMAX,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMIMIN,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMIMAX,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX2,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXB2,	0, FETCH_OP_SAMPLE_LB, tgsi_tex},
+	{TGSI_OPCODE_TXL2,	0, FETCH_OP_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_LAST,	0, ALU_OP0_NOP, tgsi_unsupported},
 };
 
 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
-	{TGSI_OPCODE_ARL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
-	{TGSI_OPCODE_MOV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-	{TGSI_OPCODE_LIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
-	{TGSI_OPCODE_RCP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_RSQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_rsq},
-	{TGSI_OPCODE_EXP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
-	{TGSI_OPCODE_LOG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
-	{TGSI_OPCODE_MUL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
-	{TGSI_OPCODE_ADD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_DP3,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DP4,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DST,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
-	{TGSI_OPCODE_MIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
-	{TGSI_OPCODE_MAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
-	{TGSI_OPCODE_SLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
-	{TGSI_OPCODE_SGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
-	{TGSI_OPCODE_MAD,	1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
-	{TGSI_OPCODE_SUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_LRP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
-	{TGSI_OPCODE_CND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARL,	0, ALU_OP0_NOP, tgsi_eg_arl},
+	{TGSI_OPCODE_MOV,	0, ALU_OP1_MOV, tgsi_op2},
+	{TGSI_OPCODE_LIT,	0, ALU_OP0_NOP, tgsi_lit},
+	{TGSI_OPCODE_RCP,	0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_RSQ,	0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
+	{TGSI_OPCODE_EXP,	0, ALU_OP0_NOP, tgsi_exp},
+	{TGSI_OPCODE_LOG,	0, ALU_OP0_NOP, tgsi_log},
+	{TGSI_OPCODE_MUL,	0, ALU_OP2_MUL, tgsi_op2},
+	{TGSI_OPCODE_ADD,	0, ALU_OP2_ADD, tgsi_op2},
+	{TGSI_OPCODE_DP3,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DP4,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DST,	0, ALU_OP0_NOP, tgsi_opdst},
+	{TGSI_OPCODE_MIN,	0, ALU_OP2_MIN, tgsi_op2},
+	{TGSI_OPCODE_MAX,	0, ALU_OP2_MAX, tgsi_op2},
+	{TGSI_OPCODE_SLT,	0, ALU_OP2_SETGT, tgsi_op2_swap},
+	{TGSI_OPCODE_SGE,	0, ALU_OP2_SETGE, tgsi_op2},
+	{TGSI_OPCODE_MAD,	1, ALU_OP3_MULADD, tgsi_op3},
+	{TGSI_OPCODE_SUB,	0, ALU_OP2_ADD, tgsi_op2},
+	{TGSI_OPCODE_LRP,	0, ALU_OP0_NOP, tgsi_lrp},
+	{TGSI_OPCODE_CND,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{20,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DP2A,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{20,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2A,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{22,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{23,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FRC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
-	{TGSI_OPCODE_CLAMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FLR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
-	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
-	{TGSI_OPCODE_EX2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_LG2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_POW,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
-	{TGSI_OPCODE_XPD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
+	{22,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{23,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FRC,	0, ALU_OP1_FRACT, tgsi_op2},
+	{TGSI_OPCODE_CLAMP,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FLR,	0, ALU_OP1_FLOOR, tgsi_op2},
+	{TGSI_OPCODE_ROUND,	0, ALU_OP1_RNDNE, tgsi_op2},
+	{TGSI_OPCODE_EX2,	0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_LG2,	0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_POW,	0, ALU_OP0_NOP, tgsi_pow},
+	{TGSI_OPCODE_XPD,	0, ALU_OP0_NOP, tgsi_xpd},
 	/* gap */
-	{32,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ABS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-	{TGSI_OPCODE_RCC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DPH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_COS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
-	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
-	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
-	{TGSI_OPCODE_KILP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* predicated kill */
-	{TGSI_OPCODE_PK2H,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK2US,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK4B,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK4UB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RFL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SEQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
-	{TGSI_OPCODE_SFL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SGT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
-	{TGSI_OPCODE_SIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
-	{TGSI_OPCODE_SLE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
-	{TGSI_OPCODE_SNE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
-	{TGSI_OPCODE_STR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_TXD,	0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
-	{TGSI_OPCODE_TXP,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_UP2H,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP2US,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP4B,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP4UB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_X2D,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ARA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ARR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
-	{TGSI_OPCODE_BRA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CAL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RET,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SSG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
-	{TGSI_OPCODE_CMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
-	{TGSI_OPCODE_SCS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
-	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
-	{TGSI_OPCODE_NRM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DP2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_TXL,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
-	{TGSI_OPCODE_BRK,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
-	{TGSI_OPCODE_IF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
+	{32,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ABS,	0, ALU_OP1_MOV, tgsi_op2},
+	{TGSI_OPCODE_RCC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DPH,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_COS,	0, ALU_OP1_COS, tgsi_trig},
+	{TGSI_OPCODE_DDX,	0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
+	{TGSI_OPCODE_DDY,	0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
+	{TGSI_OPCODE_KILP,	0, ALU_OP2_KILLGT, tgsi_kill},  /* predicated kill */
+	{TGSI_OPCODE_PK2H,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK2US,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4B,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4UB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RFL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SEQ,	0, ALU_OP2_SETE, tgsi_op2},
+	{TGSI_OPCODE_SFL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SGT,	0, ALU_OP2_SETGT, tgsi_op2},
+	{TGSI_OPCODE_SIN,	0, ALU_OP1_SIN, tgsi_trig},
+	{TGSI_OPCODE_SLE,	0, ALU_OP2_SETGE, tgsi_op2_swap},
+	{TGSI_OPCODE_SNE,	0, ALU_OP2_SETNE, tgsi_op2},
+	{TGSI_OPCODE_STR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXD,	0, FETCH_OP_SAMPLE_G, tgsi_tex},
+	{TGSI_OPCODE_TXP,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_UP2H,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP2US,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4B,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4UB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_X2D,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARR,	0, ALU_OP0_NOP, tgsi_eg_arl},
+	{TGSI_OPCODE_BRA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CAL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RET,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SSG,	0, ALU_OP0_NOP, tgsi_ssg},
+	{TGSI_OPCODE_CMP,	0, ALU_OP0_NOP, tgsi_cmp},
+	{TGSI_OPCODE_SCS,	0, ALU_OP0_NOP, tgsi_scs},
+	{TGSI_OPCODE_TXB,	0, FETCH_OP_SAMPLE_LB, tgsi_tex},
+	{TGSI_OPCODE_NRM,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DIV,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_TXL,	0, FETCH_OP_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_BRK,	0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_IF,	0, ALU_OP0_NOP, tgsi_if},
 	/* gap */
-	{75,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{76,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ELSE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
-	{TGSI_OPCODE_ENDIF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
+	{75,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{76,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ELSE,	0, ALU_OP0_NOP, tgsi_else},
+	{TGSI_OPCODE_ENDIF,	0, ALU_OP0_NOP, tgsi_endif},
 	/* gap */
-	{79,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{80,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PUSHA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_POPA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CEIL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
-	{TGSI_OPCODE_I2F,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
-	{TGSI_OPCODE_NOT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
-	{TGSI_OPCODE_TRUNC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
-	{TGSI_OPCODE_SHL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
+	{79,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{80,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PUSHA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_POPA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CEIL,	0, ALU_OP1_CEIL, tgsi_op2},
+	{TGSI_OPCODE_I2F,	0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
+	{TGSI_OPCODE_NOT,	0, ALU_OP1_NOT_INT, tgsi_op2},
+	{TGSI_OPCODE_TRUNC,	0, ALU_OP1_TRUNC, tgsi_op2},
+	{TGSI_OPCODE_SHL,	0, ALU_OP2_LSHL_INT, tgsi_op2},
 	/* gap */
-	{88,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_AND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
-	{TGSI_OPCODE_OR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
-	{TGSI_OPCODE_MOD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
-	{TGSI_OPCODE_XOR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
-	{TGSI_OPCODE_SAD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXF,	0, SQ_TEX_INST_LD, tgsi_tex},
-	{TGSI_OPCODE_TXQ,	0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
-	{TGSI_OPCODE_CONT,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
-	{TGSI_OPCODE_EMIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDPRIM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BGNLOOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
-	{TGSI_OPCODE_BGNSUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDLOOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
-	{TGSI_OPCODE_ENDSUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXQ_LZ,	0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
+	{88,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_AND,	0, ALU_OP2_AND_INT, tgsi_op2},
+	{TGSI_OPCODE_OR,	0, ALU_OP2_OR_INT, tgsi_op2},
+	{TGSI_OPCODE_MOD,	0, ALU_OP0_NOP, tgsi_imod},
+	{TGSI_OPCODE_XOR,	0, ALU_OP2_XOR_INT, tgsi_op2},
+	{TGSI_OPCODE_SAD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXF,	0, FETCH_OP_LD, tgsi_tex},
+	{TGSI_OPCODE_TXQ,	0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
+	{TGSI_OPCODE_CONT,	0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_EMIT,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDPRIM,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BGNLOOP,	0, ALU_OP0_NOP, tgsi_bgnloop},
+	{TGSI_OPCODE_BGNSUB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDLOOP,	0, ALU_OP0_NOP, tgsi_endloop},
+	{TGSI_OPCODE_ENDSUB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXQ_LZ,	0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
 	/* gap */
-	{104,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{105,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{106,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_NOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{104,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{105,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{106,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NOP,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{108,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{109,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{110,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{111,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_NRM4,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CALLNZ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_IFC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BREAKC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_KIL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* conditional kill */
-	{TGSI_OPCODE_END,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
+	{108,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{109,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{110,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{111,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NRM4,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CALLNZ,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IFC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BREAKC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_KIL,	0, ALU_OP2_KILLGT, tgsi_kill},  /* conditional kill */
+	{TGSI_OPCODE_END,	0, ALU_OP0_NOP, tgsi_end},  /* aka HALT */
 	/* gap */
-	{118,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_F2I,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_f2i},
-	{TGSI_OPCODE_IDIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
-	{TGSI_OPCODE_IMAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
-	{TGSI_OPCODE_IMIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
-	{TGSI_OPCODE_INEG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
-	{TGSI_OPCODE_ISGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
-	{TGSI_OPCODE_ISHR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
-	{TGSI_OPCODE_ISLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
-	{TGSI_OPCODE_F2U,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_f2i},
-	{TGSI_OPCODE_U2F,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
-	{TGSI_OPCODE_UADD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
-	{TGSI_OPCODE_UDIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
-	{TGSI_OPCODE_UMAD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
-	{TGSI_OPCODE_UMAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
-	{TGSI_OPCODE_UMIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
-	{TGSI_OPCODE_UMOD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
-	{TGSI_OPCODE_UMUL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
-	{TGSI_OPCODE_USEQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
-	{TGSI_OPCODE_USGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
-	{TGSI_OPCODE_USHR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
-	{TGSI_OPCODE_USLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
-	{TGSI_OPCODE_USNE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
-	{TGSI_OPCODE_SWITCH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CASE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DEFAULT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDSWITCH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{118,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_F2I,	0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
+	{TGSI_OPCODE_IDIV,	0, ALU_OP0_NOP, tgsi_idiv},
+	{TGSI_OPCODE_IMAX,	0, ALU_OP2_MAX_INT, tgsi_op2},
+	{TGSI_OPCODE_IMIN,	0, ALU_OP2_MIN_INT, tgsi_op2},
+	{TGSI_OPCODE_INEG,	0, ALU_OP2_SUB_INT, tgsi_ineg},
+	{TGSI_OPCODE_ISGE,	0, ALU_OP2_SETGE_INT, tgsi_op2},
+	{TGSI_OPCODE_ISHR,	0, ALU_OP2_ASHR_INT, tgsi_op2},
+	{TGSI_OPCODE_ISLT,	0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
+	{TGSI_OPCODE_F2U,	0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
+	{TGSI_OPCODE_U2F,	0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
+	{TGSI_OPCODE_UADD,	0, ALU_OP2_ADD_INT, tgsi_op2},
+	{TGSI_OPCODE_UDIV,	0, ALU_OP0_NOP, tgsi_udiv},
+	{TGSI_OPCODE_UMAD,	0, ALU_OP0_NOP, tgsi_umad},
+	{TGSI_OPCODE_UMAX,	0, ALU_OP2_MAX_UINT, tgsi_op2},
+	{TGSI_OPCODE_UMIN,	0, ALU_OP2_MIN_UINT, tgsi_op2},
+	{TGSI_OPCODE_UMOD,	0, ALU_OP0_NOP, tgsi_umod},
+	{TGSI_OPCODE_UMUL,	0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
+	{TGSI_OPCODE_USEQ,	0, ALU_OP2_SETE_INT, tgsi_op2},
+	{TGSI_OPCODE_USGE,	0, ALU_OP2_SETGE_UINT, tgsi_op2},
+	{TGSI_OPCODE_USHR,	0, ALU_OP2_LSHR_INT, tgsi_op2},
+	{TGSI_OPCODE_USLT,	0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
+	{TGSI_OPCODE_USNE,	0, ALU_OP2_SETNE_INT, tgsi_op2},
+	{TGSI_OPCODE_SWITCH,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CASE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DEFAULT,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDSWITCH,	0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE,    0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_I,      0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_I_MS,   0, 0, tgsi_unsupported},
@@ -6175,187 +6174,187 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SVIEWINFO,	0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
-	{TGSI_OPCODE_UARL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
-	{TGSI_OPCODE_UCMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ucmp},
+	{TGSI_OPCODE_UARL,      0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
+	{TGSI_OPCODE_UCMP,	0, ALU_OP0_NOP, tgsi_ucmp},
 	{TGSI_OPCODE_IABS,      0, 0, tgsi_iabs},
 	{TGSI_OPCODE_ISSG,      0, 0, tgsi_issg},
-	{TGSI_OPCODE_LOAD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_STORE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_MFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_LFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BARRIER,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMXCHG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMCAS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMAND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMXOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMIMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMIMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX2,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_TXB2,	0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
-	{TGSI_OPCODE_TXL2,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
-	{TGSI_OPCODE_LAST,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LOAD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_STORE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BARRIER,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUADD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMXCHG,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMCAS,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMAND,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMOR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMXOR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUMIN,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUMAX,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMIMIN,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMIMAX,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX2,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXB2,	0, FETCH_OP_SAMPLE_LB, tgsi_tex},
+	{TGSI_OPCODE_TXL2,	0, FETCH_OP_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_LAST,	0, ALU_OP0_NOP, tgsi_unsupported},
 };
 
 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
-	{TGSI_OPCODE_ARL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
-	{TGSI_OPCODE_MOV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-	{TGSI_OPCODE_LIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
-	{TGSI_OPCODE_RCP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, cayman_emit_float_instr},
-	{TGSI_OPCODE_RSQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, cayman_emit_float_instr},
-	{TGSI_OPCODE_EXP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
-	{TGSI_OPCODE_LOG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
-	{TGSI_OPCODE_MUL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
-	{TGSI_OPCODE_ADD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_DP3,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DP4,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DST,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
-	{TGSI_OPCODE_MIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
-	{TGSI_OPCODE_MAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
-	{TGSI_OPCODE_SLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
-	{TGSI_OPCODE_SGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
-	{TGSI_OPCODE_MAD,	1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
-	{TGSI_OPCODE_SUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_LRP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
-	{TGSI_OPCODE_CND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARL,	0, ALU_OP0_NOP, tgsi_eg_arl},
+	{TGSI_OPCODE_MOV,	0, ALU_OP1_MOV, tgsi_op2},
+	{TGSI_OPCODE_LIT,	0, ALU_OP0_NOP, tgsi_lit},
+	{TGSI_OPCODE_RCP,	0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
+	{TGSI_OPCODE_RSQ,	0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
+	{TGSI_OPCODE_EXP,	0, ALU_OP0_NOP, tgsi_exp},
+	{TGSI_OPCODE_LOG,	0, ALU_OP0_NOP, tgsi_log},
+	{TGSI_OPCODE_MUL,	0, ALU_OP2_MUL, tgsi_op2},
+	{TGSI_OPCODE_ADD,	0, ALU_OP2_ADD, tgsi_op2},
+	{TGSI_OPCODE_DP3,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DP4,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DST,	0, ALU_OP0_NOP, tgsi_opdst},
+	{TGSI_OPCODE_MIN,	0, ALU_OP2_MIN, tgsi_op2},
+	{TGSI_OPCODE_MAX,	0, ALU_OP2_MAX, tgsi_op2},
+	{TGSI_OPCODE_SLT,	0, ALU_OP2_SETGT, tgsi_op2_swap},
+	{TGSI_OPCODE_SGE,	0, ALU_OP2_SETGE, tgsi_op2},
+	{TGSI_OPCODE_MAD,	1, ALU_OP3_MULADD, tgsi_op3},
+	{TGSI_OPCODE_SUB,	0, ALU_OP2_ADD, tgsi_op2},
+	{TGSI_OPCODE_LRP,	0, ALU_OP0_NOP, tgsi_lrp},
+	{TGSI_OPCODE_CND,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{20,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DP2A,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{20,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2A,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{22,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{23,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FRC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
-	{TGSI_OPCODE_CLAMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FLR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
-	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
-	{TGSI_OPCODE_EX2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr},
-	{TGSI_OPCODE_LG2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr},
-	{TGSI_OPCODE_POW,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow},
-	{TGSI_OPCODE_XPD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
+	{22,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{23,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FRC,	0, ALU_OP1_FRACT, tgsi_op2},
+	{TGSI_OPCODE_CLAMP,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FLR,	0, ALU_OP1_FLOOR, tgsi_op2},
+	{TGSI_OPCODE_ROUND,	0, ALU_OP1_RNDNE, tgsi_op2},
+	{TGSI_OPCODE_EX2,	0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
+	{TGSI_OPCODE_LG2,	0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
+	{TGSI_OPCODE_POW,	0, ALU_OP0_NOP, cayman_pow},
+	{TGSI_OPCODE_XPD,	0, ALU_OP0_NOP, tgsi_xpd},
 	/* gap */
-	{32,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ABS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-	{TGSI_OPCODE_RCC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DPH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_COS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, cayman_trig},
-	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
-	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
-	{TGSI_OPCODE_KILP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* predicated kill */
-	{TGSI_OPCODE_PK2H,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK2US,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK4B,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PK4UB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RFL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SEQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
-	{TGSI_OPCODE_SFL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SGT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
-	{TGSI_OPCODE_SIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, cayman_trig},
-	{TGSI_OPCODE_SLE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
-	{TGSI_OPCODE_SNE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
-	{TGSI_OPCODE_STR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_TXD,	0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
-	{TGSI_OPCODE_TXP,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_UP2H,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP2US,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP4B,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_UP4UB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_X2D,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ARA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ARR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
-	{TGSI_OPCODE_BRA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CAL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RET,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SSG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
-	{TGSI_OPCODE_CMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
-	{TGSI_OPCODE_SCS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
-	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
-	{TGSI_OPCODE_NRM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DP2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_TXL,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
-	{TGSI_OPCODE_BRK,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
-	{TGSI_OPCODE_IF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
+	{32,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ABS,	0, ALU_OP1_MOV, tgsi_op2},
+	{TGSI_OPCODE_RCC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DPH,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_COS,	0, ALU_OP1_COS, cayman_trig},
+	{TGSI_OPCODE_DDX,	0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
+	{TGSI_OPCODE_DDY,	0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
+	{TGSI_OPCODE_KILP,	0, ALU_OP2_KILLGT, tgsi_kill},  /* predicated kill */
+	{TGSI_OPCODE_PK2H,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK2US,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4B,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4UB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RFL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SEQ,	0, ALU_OP2_SETE, tgsi_op2},
+	{TGSI_OPCODE_SFL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SGT,	0, ALU_OP2_SETGT, tgsi_op2},
+	{TGSI_OPCODE_SIN,	0, ALU_OP1_SIN, cayman_trig},
+	{TGSI_OPCODE_SLE,	0, ALU_OP2_SETGE, tgsi_op2_swap},
+	{TGSI_OPCODE_SNE,	0, ALU_OP2_SETNE, tgsi_op2},
+	{TGSI_OPCODE_STR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXD,	0, FETCH_OP_SAMPLE_G, tgsi_tex},
+	{TGSI_OPCODE_TXP,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_UP2H,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP2US,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4B,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4UB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_X2D,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARR,	0, ALU_OP0_NOP, tgsi_eg_arl},
+	{TGSI_OPCODE_BRA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CAL,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RET,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SSG,	0, ALU_OP0_NOP, tgsi_ssg},
+	{TGSI_OPCODE_CMP,	0, ALU_OP0_NOP, tgsi_cmp},
+	{TGSI_OPCODE_SCS,	0, ALU_OP0_NOP, tgsi_scs},
+	{TGSI_OPCODE_TXB,	0, FETCH_OP_SAMPLE_LB, tgsi_tex},
+	{TGSI_OPCODE_NRM,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DIV,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2,	0, ALU_OP2_DOT4, tgsi_dp},
+	{TGSI_OPCODE_TXL,	0, FETCH_OP_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_BRK,	0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_IF,	0, ALU_OP0_NOP, tgsi_if},
 	/* gap */
-	{75,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{76,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ELSE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
-	{TGSI_OPCODE_ENDIF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
+	{75,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{76,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ELSE,	0, ALU_OP0_NOP, tgsi_else},
+	{TGSI_OPCODE_ENDIF,	0, ALU_OP0_NOP, tgsi_endif},
 	/* gap */
-	{79,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{80,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_PUSHA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_POPA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CEIL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
-	{TGSI_OPCODE_I2F,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2},
-	{TGSI_OPCODE_NOT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
-	{TGSI_OPCODE_TRUNC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
-	{TGSI_OPCODE_SHL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
+	{79,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{80,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PUSHA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_POPA,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CEIL,	0, ALU_OP1_CEIL, tgsi_op2},
+	{TGSI_OPCODE_I2F,	0, ALU_OP1_INT_TO_FLT, tgsi_op2},
+	{TGSI_OPCODE_NOT,	0, ALU_OP1_NOT_INT, tgsi_op2},
+	{TGSI_OPCODE_TRUNC,	0, ALU_OP1_TRUNC, tgsi_op2},
+	{TGSI_OPCODE_SHL,	0, ALU_OP2_LSHL_INT, tgsi_op2},
 	/* gap */
-	{88,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_AND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
-	{TGSI_OPCODE_OR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
-	{TGSI_OPCODE_MOD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
-	{TGSI_OPCODE_XOR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
-	{TGSI_OPCODE_SAD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXF,	0, SQ_TEX_INST_LD, tgsi_tex},
-	{TGSI_OPCODE_TXQ,	0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
-	{TGSI_OPCODE_CONT,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
-	{TGSI_OPCODE_EMIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDPRIM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BGNLOOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
-	{TGSI_OPCODE_BGNSUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDLOOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
-	{TGSI_OPCODE_ENDSUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXQ_LZ,	0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
+	{88,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_AND,	0, ALU_OP2_AND_INT, tgsi_op2},
+	{TGSI_OPCODE_OR,	0, ALU_OP2_OR_INT, tgsi_op2},
+	{TGSI_OPCODE_MOD,	0, ALU_OP0_NOP, tgsi_imod},
+	{TGSI_OPCODE_XOR,	0, ALU_OP2_XOR_INT, tgsi_op2},
+	{TGSI_OPCODE_SAD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXF,	0, FETCH_OP_LD, tgsi_tex},
+	{TGSI_OPCODE_TXQ,	0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
+	{TGSI_OPCODE_CONT,	0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_EMIT,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDPRIM,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BGNLOOP,	0, ALU_OP0_NOP, tgsi_bgnloop},
+	{TGSI_OPCODE_BGNSUB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDLOOP,	0, ALU_OP0_NOP, tgsi_endloop},
+	{TGSI_OPCODE_ENDSUB,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXQ_LZ,	0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
 	/* gap */
-	{104,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{105,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{106,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_NOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{104,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{105,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{106,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NOP,	0, ALU_OP0_NOP, tgsi_unsupported},
 	/* gap */
-	{108,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{109,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{110,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{111,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_NRM4,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CALLNZ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_IFC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BREAKC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_KIL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* conditional kill */
-	{TGSI_OPCODE_END,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
+	{108,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{109,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{110,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{111,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NRM4,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CALLNZ,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IFC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BREAKC,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_KIL,	0, ALU_OP2_KILLGT, tgsi_kill},  /* conditional kill */
+	{TGSI_OPCODE_END,	0, ALU_OP0_NOP, tgsi_end},  /* aka HALT */
 	/* gap */
-	{118,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_F2I,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
-	{TGSI_OPCODE_IDIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
-	{TGSI_OPCODE_IMAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
-	{TGSI_OPCODE_IMIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
-	{TGSI_OPCODE_INEG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
-	{TGSI_OPCODE_ISGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
-	{TGSI_OPCODE_ISHR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
-	{TGSI_OPCODE_ISLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
-	{TGSI_OPCODE_F2U,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
-	{TGSI_OPCODE_U2F,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
-	{TGSI_OPCODE_UADD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
-	{TGSI_OPCODE_UDIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
-	{TGSI_OPCODE_UMAD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
-	{TGSI_OPCODE_UMAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
-	{TGSI_OPCODE_UMIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
-	{TGSI_OPCODE_UMOD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
-	{TGSI_OPCODE_UMUL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT, cayman_mul_int_instr},
-	{TGSI_OPCODE_USEQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
-	{TGSI_OPCODE_USGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
-	{TGSI_OPCODE_USHR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
-	{TGSI_OPCODE_USLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
-	{TGSI_OPCODE_USNE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
-	{TGSI_OPCODE_SWITCH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CASE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DEFAULT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDSWITCH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{118,			0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_F2I,	0, ALU_OP1_FLT_TO_INT, tgsi_op2},
+	{TGSI_OPCODE_IDIV,	0, ALU_OP0_NOP, tgsi_idiv},
+	{TGSI_OPCODE_IMAX,	0, ALU_OP2_MAX_INT, tgsi_op2},
+	{TGSI_OPCODE_IMIN,	0, ALU_OP2_MIN_INT, tgsi_op2},
+	{TGSI_OPCODE_INEG,	0, ALU_OP2_SUB_INT, tgsi_ineg},
+	{TGSI_OPCODE_ISGE,	0, ALU_OP2_SETGE_INT, tgsi_op2},
+	{TGSI_OPCODE_ISHR,	0, ALU_OP2_ASHR_INT, tgsi_op2},
+	{TGSI_OPCODE_ISLT,	0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
+	{TGSI_OPCODE_F2U,	0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
+	{TGSI_OPCODE_U2F,	0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
+	{TGSI_OPCODE_UADD,	0, ALU_OP2_ADD_INT, tgsi_op2},
+	{TGSI_OPCODE_UDIV,	0, ALU_OP0_NOP, tgsi_udiv},
+	{TGSI_OPCODE_UMAD,	0, ALU_OP0_NOP, tgsi_umad},
+	{TGSI_OPCODE_UMAX,	0, ALU_OP2_MAX_UINT, tgsi_op2},
+	{TGSI_OPCODE_UMIN,	0, ALU_OP2_MIN_UINT, tgsi_op2},
+	{TGSI_OPCODE_UMOD,	0, ALU_OP0_NOP, tgsi_umod},
+	{TGSI_OPCODE_UMUL,	0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
+	{TGSI_OPCODE_USEQ,	0, ALU_OP2_SETE_INT, tgsi_op2},
+	{TGSI_OPCODE_USGE,	0, ALU_OP2_SETGE_UINT, tgsi_op2},
+	{TGSI_OPCODE_USHR,	0, ALU_OP2_LSHR_INT, tgsi_op2},
+	{TGSI_OPCODE_USLT,	0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
+	{TGSI_OPCODE_USNE,	0, ALU_OP2_SETNE_INT, tgsi_op2},
+	{TGSI_OPCODE_SWITCH,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CASE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DEFAULT,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDSWITCH,	0, ALU_OP0_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE,    0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_I,      0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_I_MS,   0, 0, tgsi_unsupported},
@@ -6368,28 +6367,28 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SVIEWINFO,	0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
 	{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
-	{TGSI_OPCODE_UARL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
-	{TGSI_OPCODE_UCMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ucmp},
+	{TGSI_OPCODE_UARL,      0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
+	{TGSI_OPCODE_UCMP,	0, ALU_OP0_NOP, tgsi_ucmp},
 	{TGSI_OPCODE_IABS,      0, 0, tgsi_iabs},
 	{TGSI_OPCODE_ISSG,      0, 0, tgsi_issg},
-	{TGSI_OPCODE_LOAD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_STORE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_MFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_LFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SFENCE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BARRIER,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMXCHG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMCAS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMAND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMXOR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMUMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMIMIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ATOMIMAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX2,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-	{TGSI_OPCODE_TXB2,	0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
-	{TGSI_OPCODE_TXL2,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
-	{TGSI_OPCODE_LAST,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LOAD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_STORE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SFENCE,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BARRIER,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUADD,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMXCHG,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMCAS,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMAND,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMOR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMXOR,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUMIN,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMUMAX,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMIMIN,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ATOMIMAX,	0, ALU_OP0_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX2,	0, FETCH_OP_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXB2,	0, FETCH_OP_SAMPLE_LB, tgsi_tex},
+	{TGSI_OPCODE_TXL2,	0, FETCH_OP_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_LAST,	0, ALU_OP0_NOP, tgsi_unsupported},
 };
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index 47b4f91ee1d..4a9fa3612e1 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -27,7 +27,7 @@ void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_c
 {
 	unsigned count = (cf->ndw / 4) - 1;
 	*bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
-	*bytecode++ = cf->inst |
+	*bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) |
 			S_SQ_CF_WORD1_BARRIER(1) |
 			S_SQ_CF_WORD1_COUNT(count) |
 			S_SQ_CF_WORD1_COUNT_3(count >> 3);
@@ -56,7 +56,7 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *
 					S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
 					S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
 					S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
-					S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
+					S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
 					S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
 	} else {
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
@@ -67,7 +67,7 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *
 					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
 					S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
 					S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
-					S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
+					S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
 					S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
 			                S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
 			                S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
@@ -75,7 +75,8 @@ int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *
 	return 0;
 }
 
-void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
+void r700_bytecode_alu_read(struct r600_bytecode *bc,
+		struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
 {
 	/* WORD0 */
 	alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
@@ -105,13 +106,15 @@ void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint3
 		alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
 		alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
 		alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
-		alu->inst = G_SQ_ALU_WORD1_OP3_ALU_INST(word1);
+		alu->op = r600_isa_alu_by_opcode(bc->isa,
+				G_SQ_ALU_WORD1_OP3_ALU_INST(word1), 1);
 	}
 	else /*ALU_DWORD1_OP2*/
 	{
 		alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
 		alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
-		alu->inst = G_SQ_ALU_WORD1_OP2_ALU_INST(word1);
+		alu->op = r600_isa_alu_by_opcode(bc->isa,
+				G_SQ_ALU_WORD1_OP2_ALU_INST(word1), 0);
 		alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
 		alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
 		alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);