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authorChris Wilson <[email protected]>2017-07-31 10:56:15 +0100
committerKenneth Graunke <[email protected]>2017-08-02 18:06:35 -0700
commitfb63c43fd1b7adb5cb4f34e7616e7d564ca178e5 (patch)
treee9501d4b4a6ebd4b3736da0e65abb54fedac5d9b /src
parent858f5540786e12cbd56ede9396dc4ce1112fe9db (diff)
i965/blit: Remember to include miptree buffer offset in relocs
Remember to add the offset to the start of the buffer in the relocation or else we write 0xff into random bytes elsewhere. Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c4
-rw-r--r--src/mesa/drivers/dri/i965/intel_pixel_bitmap.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index b1db7aa2293..a9cdf489f15 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -830,11 +830,11 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
if (brw->gen >= 8) {
OUT_RELOC64(mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ mt->offset + offset);
} else {
OUT_RELOC(mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ mt->offset + offset);
}
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index aeea3c8bd6a..8d467adc56e 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -294,7 +294,7 @@ do_blit_bitmap( struct gl_context *ctx,
color,
irb->mt->surf.row_pitch,
irb->mt->bo,
- 0,
+ irb->mt->offset,
irb->mt->surf.tiling,
dstx + px,
dsty + py,