diff options
author | Chia-I Wu <[email protected]> | 2014-09-25 12:44:53 +0800 |
---|---|---|
committer | Chia-I Wu <[email protected]> | 2014-09-26 21:15:55 +0800 |
commit | f1662e3670c576fb2f1abe96e5855c80d22128f3 (patch) | |
tree | d57f953557593619fca777f9cae894634c0a926b /src | |
parent | 7fc74153166ea59d72083f9a09e9ddb966a23985 (diff) |
ilo: sanity check ilo_render_get_*_len()
Assert that we never write more than what ilo_render_get_*_len() returns.
Signed-off-by: Chia-I Wu <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/gallium/drivers/ilo/ilo_render.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/gallium/drivers/ilo/ilo_render.c b/src/gallium/drivers/ilo/ilo_render.c index 2995ee8346f..b9ea32c5fb9 100644 --- a/src/gallium/drivers/ilo/ilo_render.c +++ b/src/gallium/drivers/ilo/ilo_render.c @@ -215,6 +215,7 @@ ilo_render_emit_flush(struct ilo_render *render) GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE | GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | GEN6_PIPE_CONTROL_CS_STALL; + const unsigned batch_used = ilo_builder_batch_used(render->builder); ILO_DEV_ASSERT(render->dev, 6, 7.5); @@ -225,6 +226,9 @@ ilo_render_emit_flush(struct ilo_render *render) render->state.current_pipe_control_dw1 |= dw1; render->state.deferred_pipe_control_dw1 &= ~dw1; + + assert(ilo_builder_batch_used(render->builder) <= batch_used + + ilo_render_get_flush_len(render)); } /** @@ -300,6 +304,7 @@ ilo_render_emit_query(struct ilo_render *render, (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ? GEN7_REG_SO_NUM_PRIMS_WRITTEN(q->index) : GEN6_REG_SO_NUM_PRIMS_WRITTEN; + const unsigned batch_used = ilo_builder_batch_used(render->builder); const uint32_t *regs; int reg_count = 0, i; uint32_t pipe_control_dw1 = 0; @@ -332,6 +337,8 @@ ilo_render_emit_query(struct ilo_render *render, } if (pipe_control_dw1) { + assert(!reg_count); + if (ilo_dev_gen(render->dev) == ILO_GEN(6)) gen6_wa_pre_pipe_control(render, pipe_control_dw1); @@ -340,13 +347,10 @@ ilo_render_emit_query(struct ilo_render *render, render->state.current_pipe_control_dw1 |= pipe_control_dw1; render->state.deferred_pipe_control_dw1 &= ~pipe_control_dw1; + } else if (reg_count) { + ilo_render_emit_flush(render); } - if (!reg_count) - return; - - ilo_render_emit_flush(render); - for (i = 0; i < reg_count; i++) { if (regs[i]) { /* store lower 32 bits */ @@ -360,4 +364,7 @@ ilo_render_emit_query(struct ilo_render *render, offset += 8; } + + assert(ilo_builder_batch_used(render->builder) <= batch_used + + ilo_render_get_query_len(render, q->type)); } |