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authorJason Ekstrand <[email protected]>2017-09-01 22:20:23 -0700
committerJason Ekstrand <[email protected]>2017-10-25 16:14:09 -0700
commitd24311b7b55d1dec1ce85e046619d05fa96ed99e (patch)
tree80e308445046d1db80dfac1d011ffcee1d654ebd /src
parentece206b84864e3727bee2672b838f70f2a3f460c (diff)
intel/compiler: Call nir_lower_system_values in brw_preprocess_nir
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_nir.c2
-rw-r--r--src/intel/vulkan/anv_pipeline.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c2
3 files changed, 2 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 327216eaaa7..e5ff6deb2f7 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -635,6 +635,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
/* Lower a bunch of stuff */
OPT(nir_lower_var_copies);
+ OPT(nir_lower_system_values);
+
OPT(nir_lower_clip_cull_distance_arrays);
nir_variable_mode indirect_mask = 0;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 9863ec334e3..8a2e4f83ca7 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -194,8 +194,6 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
nir = brw_preprocess_nir(compiler, nir);
- NIR_PASS_V(nir, nir_lower_system_values);
-
if (stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, anv_nir_lower_input_attachments);
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index ebb6998a002..6925121778a 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -89,8 +89,6 @@ brw_create_nir(struct brw_context *brw,
nir = brw_preprocess_nir(brw->screen->compiler, nir);
- NIR_PASS_V(nir, nir_lower_system_values);
-
if (stage == MESA_SHADER_FRAGMENT) {
static const struct nir_lower_wpos_ytransform_options wpos_options = {
.state_tokens = {STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0},