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authorDave Airlie <[email protected]>2017-08-21 21:08:10 +0100
committerDave Airlie <[email protected]>2017-09-06 03:22:22 +0100
commit6d929d3f85604768971d04fa2548f02ffca1696e (patch)
tree596f9aad5cb3f320454216675bc759baa99bb7b1 /src
parentd118ff876559e468d2d243470947eee53171fe57 (diff)
radv/gfx9: set descriptor up for base_mip to level range.
This is required on GFX9, fixes a bug in Talos where all the mipmaps overlay each other. Just pushing this as well as it fixes Talos. Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/radv_image.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 06b9c2f9d37..9c5767262e1 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -876,6 +876,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
uint32_t blk_w;
uint32_t *descriptor;
uint32_t *fmask_descriptor;
+ uint32_t hw_level = 0;
if (is_storage_image) {
descriptor = iview->storage_descriptor;
@@ -888,11 +889,13 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ hw_level = iview->base_mip;
si_make_texture_descriptor(device, image, is_storage_image,
iview->type,
iview->vk_format,
components,
- 0, iview->level_count - 1,
+ hw_level, hw_level + iview->level_count - 1,
iview->base_layer,
iview->base_layer + iview->layer_count - 1,
iview->extent.width,