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authorNanley Chery <[email protected]>2015-06-18 11:02:17 -0700
committerNanley Chery <[email protected]>2015-08-26 14:36:43 -0700
commit1a9ceed4ba764cf73a643f8f2135b5b84cfe4581 (patch)
tree06c96d1497bdd7e3955382ddec8b182d47ea31ae /src
parent10ff64fd3d19bc9da793fa43eb746c29608bfddd (diff)
i965: correct mt->align_h for 2D textures on Skylake
In agreement with commit 4ab8d59a23, vertical alignment values are equal to four times the block height on Gen9+. v2: add newlines to separate declarations, statments, and comments. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1d8eb090556..e8a92dde8a9 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -270,9 +270,14 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
* Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE "Surface Vertical Alignment" field.
*/
- if (_mesa_is_format_compressed(mt->format))
- /* See comment above for the horizontal alignment */
- return brw->gen >= 9 ? 16 : 4;
+ if (_mesa_is_format_compressed(mt->format)) {
+ unsigned int i, j;
+
+ _mesa_get_format_block_size(mt->format, &i, &j);
+
+ /* See comment above for the horizontal alignment */
+ return brw->gen >= 9 ? j * 4 : 4;
+ }
if (mt->format == MESA_FORMAT_S_UINT8)
return brw->gen >= 7 ? 8 : 4;