diff options
| author | James Legg <[email protected]> | 2018-02-22 16:57:53 +0000 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2018-03-20 16:57:24 +0000 |
| commit | 046145ae81c546e1410d9077700aebbbceb7b029 (patch) | |
| tree | dcdcce20e32c1b246287920e70b471c40d096b1c /src | |
| parent | bb51eb535566914124015c7a332ac5de42418f11 (diff) | |
radv: Really use correct HTILE expanded words.
When transitioning to an htile compressed depth format, Set the full
depth range, so later rasterization can pass HiZ. Previously, for depth
only formats, the depth range was set to 0 to 0. This caused unwanted
HiZ rejections with a VK_FORMAT_D16_UNORM depth buffer
(VK_FORMAT_D32_SFLOAT was not affected somehow).
These values are derived from PAL [0], since I can't find the
specification describing the htile values.
[0] https://github.com/GPUOpen-Drivers/pal/blob/5cba4ecbda9452773f59692f5915301e7db4a183/src/core/hw/gfxip/gfx9/gfx9MaskRam.cpp#L1500
CC: Dave Airlie <[email protected]>
CC: Bas Nieuwenhuizen <[email protected]>
CC: [email protected]
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Tested-by: Grazvydas Ignotas <[email protected]>
Fixes: 5158603182fe7435 "radv: Use correct HTILE expanded words."
(cherry picked from commit afd8fd0656a8eb3a2ce892381387aad3c6b0a78f)
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4bf0d88bc84..777f3dc4c9a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3896,8 +3896,8 @@ void radv_CmdEndRenderPass( /* * For HTILE we have the following interesting clear words: - * 0x0000030f: Uncompressed for depth+stencil HTILE. - * 0x0000000f: Uncompressed for depth only HTILE. + * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE + * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE. * 0xfffffff0: Clear depth to 1.0 * 0x00000000: Clear depth to 0.0 */ @@ -3945,7 +3945,7 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe radv_initialize_htile(cmd_buffer, image, range, 0); } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) && radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) { - uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf; + uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f; radv_initialize_htile(cmd_buffer, image, range, clear_value); } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) && !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) { |