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authorDamien Lespiau <[email protected]>2013-02-27 15:05:24 +0000
committerKristian Høgsberg <[email protected]>2014-12-08 16:33:59 -0800
commit5bad948fa8a4fe812d254b6251e5e5dbd8a64e1c (patch)
treeaf98a61f453c53b5a52a69ccab50f4cfcc1481f9 /src
parent9404494b9be5d44e6b858c482021b3edcaf87b7a (diff)
i965/skl: Emit depth stall workaround for gen9 as well
The docs say that we shouldn't need this workaround for gen8+, but just removing it, causes gpu hangs. We'll revisit this, but for now, just extend the workaround to gen9. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index cd45af6fbe2..2bd11d7a63e 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -535,7 +535,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
void
intel_emit_depth_stall_flushes(struct brw_context *brw)
{
- assert(brw->gen >= 6 && brw->gen <= 8);
+ assert(brw->gen >= 6 && brw->gen <= 9);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);