i965: Add support for Z16 depth formats.

This is a squash of the following two commits.  The first caused a
regression on SNB systems without a HiZ capable DDX, and the second
fixes that regression.

    i965: Add support for Z16 depth formats.

    v2: Don't flag the format as being HiZ ready (there's DRI2 handshake
        pain to go through).

    Fixes piglit gl-3.0-required-sized-texture-formats

    NOTE: This is a candidate for the 8.0 branch.

    Reviewed-by: Kenneth Graunke <[email protected]>
    Reviewed-by: Chad Versace <[email protected]>
    (cherry picked from commit 2f868f1ddd636bc8d4cbcd5beeef1246cec80c65)

    intel/gen6: Some framebuffers having separate depthstencil should be unsupported

    When the framebuffer has separate depth and stencil buffers, and HiZ is
    not enabled on the depth buffer, mark the framebuffer as unsupported. This
    happens when trying to create a framebuffer with Z16/S8 because we haven't
    enabled HiZ on Z16 yet.

    Fixes gles2conform test stencil8.

    Note: This is a candiate for the 8.0 branch.
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44948
    Reviewed-and-tested-by: Ian Romanick <[email protected]>
    Reviewed--by: Eric Anholt <[email protected]>
    Signed-off-by: Chad Versace <[email protected]>
    (cherry picked from commit ba5252e590782a77b8a46d9c0ec4691cf8da6298)

2 files changed, 10 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index b40f5e1b87a..b7454b0abeb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -553,6 +553,7 @@ brw_init_surface_formats(struct brw_context *brw)
    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
+   ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 }
 
 bool
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index c37075c6be9..45a682727e4 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -804,6 +804,15 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 	    fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
 	 if (stencil_mt->format != MESA_FORMAT_S8)
 	    fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
+	 if (intel->gen < 7 && depth_mt->hiz_mt == NULL) {
+	    /* Before Gen7, separate depth and stencil buffers can be used
+	     * only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
+	     * Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
+	     *     [DevSNB]: This field must be set to the same value (enabled
+	     *     or disabled) as Hierarchical Depth Buffer Enable.
+	     */
+	    fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED;
+	 }
       }
    }