i965/Gen8: Set up layer constraints properly for depth buffers

Same issues as the previous commit fixed for Gen7:
- Bogus physical->logical layer conversion; depth/stencil surfaces
  are still IMS layout on Gen8.
- mt_layer ignored in layered rendering case, which breaks handling
  of views with MinLayer.
- Render target array extent not set correctly for arrays.

I'm not able to test this one since I can't get a Broadwell yet, but
it's the same set of fixes as for Gen7.

V2: Restore the MAX2() to account for zero depth/layer_count.

Signed-off-by: Chris Forbes <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

1 files changed, 6 insertions, 9 deletions

diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index f6031e97231..31d6d565f08 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -168,7 +168,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
    rb = (struct gl_renderbuffer *) irb;
 
    if (rb) {
-      depth = MAX2(rb->Depth, 1);
+      depth = MAX2(irb->layer_count, 1);
       if (rb->TexImage)
          gl_target = rb->TexImage->TexObject->Target;
    }
@@ -184,19 +184,16 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
       surftype = BRW_SURFACE_2D;
       depth *= 6;
       break;
+   case GL_TEXTURE_3D:
+      assert(rb);
+      depth = MAX2(rb->Depth, 1);
+      /* fallthrough */
    default:
       surftype = translate_tex_target(gl_target);
       break;
    }
 
-   if (fb->MaxNumLayers > 0 || !irb) {
-      min_array_element = 0;
-   } else if (irb->mt->num_samples > 1) {
-      /* Convert physical to logical layer. */
-      min_array_element = irb->mt_layer / irb->mt->num_samples;
-   } else {
-      min_array_element = irb->mt_layer;
-   }
+   min_array_element = irb ? irb->mt_layer : 0;
 
    lod = irb ? irb->mt_level - irb->mt->first_level : 0;