r600g: add support for all R6XX/R7XX asic

This configure some of the value properly based on
asic so others asic than RV710 works too.

Signed-off-by: Jerome Glisse <[email protected]>

4 files changed, 316 insertions, 87 deletions

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 0a7efe3bfb9..05575b57676 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -32,6 +32,7 @@
 #include "r600_resource.h"
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600d.h"
 
 static void r600_destroy_context(struct pipe_context *context)
 {
@@ -62,6 +63,245 @@ static void r600_flush(struct pipe_context *ctx, unsigned flags,
 	dc++;
 }
 
+static void r600_init_config(struct r600_context *rctx)
+{
+	int ps_prio;
+	int vs_prio;
+	int gs_prio;
+	int es_prio;
+	int num_ps_gprs;
+	int num_vs_gprs;
+	int num_gs_gprs;
+	int num_es_gprs;
+	int num_temp_gprs;
+	int num_ps_threads;
+	int num_vs_threads;
+	int num_gs_threads;
+	int num_es_threads;
+	int num_ps_stack_entries;
+	int num_vs_stack_entries;
+	int num_gs_stack_entries;
+	int num_es_stack_entries;
+	enum radeon_family family;
+
+	family = radeon_get_family(rctx->rw);
+	ps_prio = 0;
+	vs_prio = 1;
+	gs_prio = 2;
+	es_prio = 3;
+	switch (family) {
+	case CHIP_R600:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 40;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	default:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV670:
+		num_ps_gprs = 144;
+		num_vs_gprs = 40;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV770:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 256;
+		num_vs_stack_entries = 256;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV730:
+	case CHIP_RV740:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV710:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 48;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	}
+	printf("ps_prio : %d\n", ps_prio);
+	printf("vs_prio : %d\n", vs_prio);
+	printf("gs_prio : %d\n", gs_prio);
+	printf("es_prio : %d\n", es_prio);
+	printf("num_ps_gprs : %d\n", num_ps_gprs);
+	printf("num_vs_gprs : %d\n", num_vs_gprs);
+	printf("num_gs_gprs : %d\n", num_gs_gprs);
+	printf("num_es_gprs : %d\n", num_es_gprs);
+	printf("num_temp_gprs : %d\n", num_temp_gprs);
+	printf("num_ps_threads : %d\n", num_ps_threads);
+	printf("num_vs_threads : %d\n", num_vs_threads);
+	printf("num_gs_threads : %d\n", num_gs_threads);
+	printf("num_es_threads : %d\n", num_es_threads);
+	printf("num_ps_stack_entries : %d\n", num_ps_stack_entries);
+	printf("num_vs_stack_entries : %d\n", num_vs_stack_entries);
+	printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
+	printf("num_es_stack_entries : %d\n", num_es_stack_entries);
+
+	rctx->config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	switch (family) {
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV710:
+		break;
+	default:
+		rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		break;
+	}
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+
+	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+
+	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+
+	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+
+	rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(rctx->config);
+}
+
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 {
 	struct r600_context *rctx = CALLOC_STRUCT(r600_context);
@@ -107,49 +347,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
 	radeon_state_pm4(rctx->cb_cntl);
 
-	rctx->config = radeon_state(rscreen->rw, R600_CONFIG_TYPE, R600_CONFIG);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0xE400000C;
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0x403800C0;
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0x00003090;
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0x00800080;
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(rctx->config);
+	r600_init_config(rctx);
 
 	rctx->ctx = radeon_ctx(rscreen->rw);
 	rctx->draw = radeon_draw(rscreen->rw);
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index 71aa09719e0..447ba98f004 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -580,27 +580,5 @@
 #define   S_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) & 0x7) << 29)
 #define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
 #define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
-#define P_SQ_ALU_WORD1_OP2_V2
-#define   S_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x)                          (((x) & 0x1) << 0)
-#define   G_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x)                          (((x) >> 0) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_SRC0_ABS                             0xFFFFFFFE
-#define   S_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x)                          (((x) & 0x1) << 1)
-#define   G_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x)                          (((x) >> 1) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_SRC1_ABS                             0xFFFFFFFD
-#define   S_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x)               (((x) & 0x1) << 2)
-#define   G_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x)               (((x) >> 2) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK                  0xFFFFFFFB
-#define   S_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x)                       (((x) & 0x1) << 3)
-#define   G_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x)                       (((x) >> 3) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED                          0xFFFFFFF7
-#define   S_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x)                        (((x) & 0x1) << 4)
-#define   G_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x)                        (((x) >> 4) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_WRITE_MASK                           0xFFFFFFEF
-#define   S_SQ_ALU_WORD1_OP2_V2_OMOD(x)                              (((x) & 0x3) << 5)
-#define   G_SQ_ALU_WORD1_OP2_V2_OMOD(x)                              (((x) >> 5) & 0x3)
-#define   C_SQ_ALU_WORD1_OP2_V2_OMOD                                 0xFFFFFF9F
-#define   S_SQ_ALU_WORD1_OP2_V2_ALU_INST(x)                          (((x) & 0x7FF) << 7)
-#define   G_SQ_ALU_WORD1_OP2_V2_ALU_INST(x)                          (((x) >> 7) & 0x7FF)
-#define   C_SQ_ALU_WORD1_OP2_V2_ALU_INST                             0xFFFC007F
 
 #endif
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index d2c7248ff2b..44834984c68 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -81,6 +81,81 @@
 #define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count))
 
 /* Registers */
+#define R_008C00_SQ_CONFIG                           0x00008C00
+#define   S_008C00_VC_ENABLE(x)                        (((x) & 0x1) << 0)
+#define   G_008C00_VC_ENABLE(x)                        (((x) >> 0) & 0x1)
+#define   C_008C00_VC_ENABLE(x)                        0xFFFFFFFE
+#define   S_008C00_EXPORT_SRC_C(x)                     (((x) & 0x1) << 1)
+#define   G_008C00_EXPORT_SRC_C(x)                     (((x) >> 1) & 0x1)
+#define   C_008C00_EXPORT_SRC_C(x)                     0xFFFFFFFD
+#define   S_008C00_DX9_CONSTS(x)                       (((x) & 0x1) << 2)
+#define   G_008C00_DX9_CONSTS(x)                       (((x) >> 2) & 0x1)
+#define   C_008C00_DX9_CONSTS(x)                       0xFFFFFFFB
+#define   S_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) & 0x1) << 3)
+#define   G_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) >> 3) & 0x1)
+#define   C_008C00_ALU_INST_PREFER_VECTOR(x)           0xFFFFFFF7
+#define   S_008C00_DX10_CLAMP(x)                       (((x) & 0x1) << 4)
+#define   G_008C00_DX10_CLAMP(x)                       (((x) >> 4) & 0x1)
+#define   C_008C00_DX10_CLAMP(x)                       0xFFFFFFEF
+#define   S_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) & 0x3) << 8)
+#define   G_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) >> 8) & 0x3)
+#define   C_008C00_CLAUSE_SEQ_PRIO(x)                  0xFFFFFCFF
+#define   S_008C00_PS_PRIO(x)                          (((x) & 0x3) << 24)
+#define   G_008C00_PS_PRIO(x)                          (((x) >> 24) & 0x3)
+#define   C_008C00_PS_PRIO(x)                          0xFCFFFFFF
+#define   S_008C00_VS_PRIO(x)                          (((x) & 0x3) << 26)
+#define   G_008C00_VS_PRIO(x)                          (((x) >> 26) & 0x3)
+#define   C_008C00_VS_PRIO(x)                          0xF3FFFFFF
+#define   S_008C00_GS_PRIO(x)                          (((x) & 0x3) << 28)
+#define   G_008C00_GS_PRIO(x)                          (((x) >> 28) & 0x3)
+#define   C_008C00_GS_PRIO(x)                          0xCFFFFFFF
+#define   S_008C00_ES_PRIO(x)                          (((x) & 0x3) << 30)
+#define   G_008C00_ES_PRIO(x)                          (((x) >> 30) & 0x3)
+#define   C_008C00_ES_PRIO(x)                          0x3FFFFFFF
+#define R_008C04_SQ_GPR_RESOURCE_MGMT_1              0x00008C04
+#define   S_008C04_NUM_PS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C04_NUM_PS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C04_NUM_PS_GPRS(x)                      0xFFFFFF00
+#define   S_008C04_NUM_VS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C04_NUM_VS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C04_NUM_VS_GPRS(x)                      0xFF00FFFF
+#define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
+#define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
+#define   C_008C04_NUM_CLAUSE_TEMP_GPRS(x)             0x0FFFFFFF
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x00008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS(x)                      0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS(x)                      0xFF00FFFF
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x00008C0C
+#define   S_008C0C_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C0C_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C0C_NUM_PS_THREADS(x)                   0xFFFFFF00
+#define   S_008C0C_NUM_VS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C0C_NUM_VS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C0C_NUM_VS_THREADS(x)                   0xFFFF00FF
+#define   S_008C0C_NUM_GS_THREADS(x)                   (((x) & 0xFF) << 16)
+#define   G_008C0C_NUM_GS_THREADS(x)                   (((x) >> 16) & 0xFF)
+#define   C_008C0C_NUM_GS_THREADS(x)                   0xFF00FFFF
+#define   S_008C0C_NUM_ES_THREADS(x)                   (((x) & 0xFF) << 24)
+#define   G_008C0C_NUM_ES_THREADS(x)                   (((x) >> 24) & 0xFF)
+#define   C_008C0C_NUM_ES_THREADS(x)                   0x00FFFFFF
+#define R_008C10_SQ_STACK_RESOURCE_MGMT_1            0x00008C10
+#define   S_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C10_NUM_PS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C10_NUM_VS_STACK_ENTRIES(x)             0xF000FFFF
+#define R_008C14_SQ_STACK_RESOURCE_MGMT_2            0x00008C14
+#define   S_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C14_NUM_GS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C14_NUM_ES_STACK_ENTRIES(x)             0xF000FFFF
 #define R_0280A0_CB_COLOR0_INFO                      0x0280A0
 #define   S_0280A0_ENDIAN(x)                           (((x) & 0x3) << 0)
 #define   G_0280A0_ENDIAN(x)                           (((x) >> 0) & 0x3)
diff --git a/src/gallium/drivers/r600/r700_sq.h b/src/gallium/drivers/r600/r700_sq.h
index 8266af6d1fc..9a117aeb1d3 100644
--- a/src/gallium/drivers/r600/r700_sq.h
+++ b/src/gallium/drivers/r600/r700_sq.h
@@ -583,27 +583,5 @@
 #define   S_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) & 0x7) << 29)
 #define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
 #define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
-#define P_SQ_ALU_WORD1_OP2_V2
-#define   S_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x)                          (((x) & 0x1) << 0)
-#define   G_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x)                          (((x) >> 0) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_SRC0_ABS                             0xFFFFFFFE
-#define   S_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x)                          (((x) & 0x1) << 1)
-#define   G_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x)                          (((x) >> 1) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_SRC1_ABS                             0xFFFFFFFD
-#define   S_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x)               (((x) & 0x1) << 2)
-#define   G_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x)               (((x) >> 2) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK                  0xFFFFFFFB
-#define   S_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x)                       (((x) & 0x1) << 3)
-#define   G_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x)                       (((x) >> 3) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED                          0xFFFFFFF7
-#define   S_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x)                        (((x) & 0x1) << 4)
-#define   G_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x)                        (((x) >> 4) & 0x1)
-#define   C_SQ_ALU_WORD1_OP2_V2_WRITE_MASK                           0xFFFFFFEF
-#define   S_SQ_ALU_WORD1_OP2_V2_OMOD(x)                              (((x) & 0x3) << 5)
-#define   G_SQ_ALU_WORD1_OP2_V2_OMOD(x)                              (((x) >> 5) & 0x3)
-#define   C_SQ_ALU_WORD1_OP2_V2_OMOD                                 0xFFFFFF9F
-#define   S_SQ_ALU_WORD1_OP2_V2_ALU_INST(x)                          (((x) & 0x7FF) << 7)
-#define   G_SQ_ALU_WORD1_OP2_V2_ALU_INST(x)                          (((x) >> 7) & 0x7FF)
-#define   C_SQ_ALU_WORD1_OP2_V2_ALU_INST                             0xFFFC007F
 
 #endif