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authorKenneth Graunke <[email protected]>2019-06-19 23:12:52 -0500
committerKenneth Graunke <[email protected]>2019-06-20 13:32:16 -0500
commitecc500398f29c2dd7a86de7dec20f121974c65a2 (patch)
treefd1b123b4e7368f782a421545848aed5fda8c9ba /src
parent1d63af0f2c6be12d134357670c32c47ace2c8da2 (diff)
iris: Drop RT flushes from depth stencil clearing flushes.
These write depth and stencil, not color writes, so there's no need to flush the render target.
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/iris/iris_blit.c2
-rw-r--r--src/gallium/drivers/iris/iris_clear.c5
-rw-r--r--src/gallium/drivers/iris/iris_resource.c9
-rw-r--r--src/gallium/drivers/iris/iris_resource.h1
4 files changed, 8 insertions, 9 deletions
diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c
index 1ac56aa4eaf..6f90910b516 100644
--- a/src/gallium/drivers/iris/iris_blit.c
+++ b/src/gallium/drivers/iris/iris_blit.c
@@ -493,6 +493,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *)
info->dst.resource,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH,
"cache history: post-blit");
}
@@ -640,6 +641,7 @@ iris_resource_copy_region(struct pipe_context *ctx,
}
iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *) dst,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH,
"cache history: post copy_region");
}
diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c
index 23348077d31..1724a35c54e 100644
--- a/src/gallium/drivers/iris/iris_clear.c
+++ b/src/gallium/drivers/iris/iris_clear.c
@@ -349,6 +349,7 @@ clear_color(struct iris_context *ice,
blorp_batch_finish(&blorp_batch);
iris_flush_and_dirty_for_history(ice, batch, res,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH,
"cache history: post color clear");
iris_resource_finish_render(ice, res, level,
@@ -515,7 +516,7 @@ clear_depth_stencil(struct iris_context *ice,
if (z_res && clear_depth &&
can_fast_clear_depth(ice, z_res, level, box, depth)) {
fast_clear_depth(ice, z_res, level, box, depth);
- iris_flush_and_dirty_for_history(ice, batch, res,
+ iris_flush_and_dirty_for_history(ice, batch, res, 0,
"cache history: post fast Z clear");
clear_depth = false;
z_res = false;
@@ -552,7 +553,7 @@ clear_depth_stencil(struct iris_context *ice,
clear_stencil && stencil_res ? 0xff : 0, stencil);
blorp_batch_finish(&blorp_batch);
- iris_flush_and_dirty_for_history(ice, batch, res,
+ iris_flush_and_dirty_for_history(ice, batch, res, 0,
"cache history: post slow ZS clear");
if (z_res) {
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 8ca1e6e940a..9a2b7bda22b 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -1572,18 +1572,13 @@ void
iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res,
+ uint32_t extra_flags,
const char *reason)
{
if (res->base.target != PIPE_BUFFER)
return;
- uint32_t flush = iris_flush_bits_for_history(res);
-
- /* We've likely used the rendering engine (i.e. BLORP) to write to this
- * surface. Flush the render cache so the data actually lands.
- */
- if (batch->name != IRIS_BATCH_COMPUTE)
- flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
+ uint32_t flush = iris_flush_bits_for_history(res) | extra_flags;
iris_emit_pipe_control_flush(batch, reason, flush);
diff --git a/src/gallium/drivers/iris/iris_resource.h b/src/gallium/drivers/iris/iris_resource.h
index 419122c8bbd..75f04d492d9 100644
--- a/src/gallium/drivers/iris/iris_resource.h
+++ b/src/gallium/drivers/iris/iris_resource.h
@@ -268,6 +268,7 @@ uint32_t iris_flush_bits_for_history(struct iris_resource *res);
void iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res,
+ uint32_t extra_flags,
const char *reason);
unsigned iris_get_num_logical_layers(const struct iris_resource *res,