diff options
| author | Anuj Phogat <[email protected]> | 2019-03-26 15:45:29 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2019-03-28 19:59:59 +0000 |
| commit | e0f4359ec12e8e8dcd96d658b8ef3e308ffe8859 (patch) | |
| tree | e6afd2e220a8a842d409cab822f0eed73ce39ea2 /src | |
| parent | 78825ca2d05357d159ecd4df31bfddf232bc53a1 (diff) | |
iris/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set.
See Mesa commit 5eb173304bd.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 1ae9c557a27..ddce0023dbe 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -707,6 +707,13 @@ iris_init_render_context(struct iris_screen *screen, } iris_emit_lri(batch, SAMPLER_MODE, reg_val); + /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */ + iris_pack_state(GENX(HALF_SLICE_CHICKEN7), ®_val, reg) { + reg.EnabledTexelOffsetPrecisionFix = 1; + reg.EnabledTexelOffsetPrecisionFixMask = 1; + } + iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val); + // XXX: 3D_MODE? #endif |