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authorTom Stellard <thomas.stellard@amd.com>2012-09-05 11:30:16 -0400
committerTom Stellard <thomas.stellard@amd.com>2012-09-05 13:17:49 -0400
commitd220e2de7fe7a75e70d68f2a4169103020fa7ca6 (patch)
treee15d48558e0c421903d7ba836fc1472692a2b640 /src
parent12d3d6f6ab34d0ede8a2798fe68e7c9b1c894dac (diff)
radeon/llvm: Fix operand ordering for V_CNDMASK_B32
This fixes several hundred piglit tests.
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeon/SIInstructions.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 39ecdcd0102..20d4c003aa1 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -674,15 +674,15 @@ def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16",
def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst),
(ins AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc), "V_CNDMASK_B32",
[(set (i32 VReg_32:$dst),
- (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > {
+ (select VCCReg:$vcc, VReg_32:$src1, AllReg_32:$src0))] > {
let DisableEncoding = "$vcc";
}
//f32 pattern for V_CNDMASK_B32
def : Pat <
- (f32 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)),
- (V_CNDMASK_B32 AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc)
+ (f32 (select VCCReg:$vcc, VReg_32:$src0, AllReg_32:$src1)),
+ (V_CNDMASK_B32 AllReg_32:$src1, VReg_32:$src0, VCCReg:$vcc)
>;
defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;