diff options
| author | Marek Olšák <[email protected]> | 2019-07-16 23:17:38 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-19 20:16:56 -0400 |
| commit | bcabf75ab7d044e516aa5f92e0b7dc49cfa29d7c (patch) | |
| tree | 3557d7257f6f76e32515e352cf68ad0a11ce7b63 /src | |
| parent | 47f41af06c7eb1cc7e99b3d384a089cf94fd3728 (diff) | |
radeonsi: initialize scissor registers etc. without clear state
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Acked-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 1de54885ce7..398dc83a924 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5455,7 +5455,7 @@ static void si_init_config(struct si_context *sctx) /* CLEAR_STATE doesn't clear these correctly on certain generations. * I don't know why. Deduced by trial and error. */ - if (sctx->chip_class <= GFX7) { + if (sctx->chip_class <= GFX7 || !has_clear_state) { si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); |