diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-25 13:25:32 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-07-07 17:03:39 +0200 |
| commit | b144a70ca832909d6c6ffb52c8f4ee6880f0e1f7 (patch) | |
| tree | 770bd50efbc19a6f85eba2ac0af23d821b5974e2 /src | |
| parent | 5551d6d6ea0163e223e9c5e8d5201ae8ef12be26 (diff) | |
radv/gfx10: implement radv_pipeline_generate_geometry_shader()
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 79d71d2259e..44de1aad674 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3210,9 +3210,15 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, va = radv_buffer_get_va(gs->bo) + gs->bo_offset; if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { - radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2); - radeon_emit(cs, va >> 8); - radeon_emit(cs, S_00B214_MEM_BASE(va >> 40)); + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); + radeon_emit(cs, va >> 8); + radeon_emit(cs, S_00B324_MEM_BASE(va >> 40)); + } else { + radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2); + radeon_emit(cs, va >> 8); + radeon_emit(cs, S_00B214_MEM_BASE(va >> 40)); + } radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); radeon_emit(cs, gs->config.rsrc1); |