i965: Move brw_get_rb_for_slice to brw_meta_util

Reviewed-by: Topi Pohjolainen <[email protected]>

4 files changed, 52 insertions, 49 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 035cbe9d325..69cedbc2faf 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1372,11 +1372,6 @@ GLboolean brwCreateContext(gl_api api,
 /*======================================================================
  * brw_misc_state.c
  */
-struct gl_renderbuffer *brw_get_rb_for_slice(struct brw_context *brw,
-                                             struct intel_mipmap_tree *mt,
-                                             unsigned level, unsigned layer,
-                                             bool flat);
-
 void brw_meta_updownsample(struct brw_context *brw,
                            struct intel_mipmap_tree *src,
                            struct intel_mipmap_tree *dst);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
index f5fc2072dd7..91c92bdbacd 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
@@ -24,6 +24,7 @@
 #include "brw_context.h"
 #include "intel_batchbuffer.h"
 #include "intel_fbo.h"
+#include "brw_meta_util.h"
 
 #include "main/blit.h"
 #include "main/buffers.h"
@@ -42,50 +43,6 @@
  */
 
 /**
- * Creates a new named renderbuffer that wraps the first slice
- * of an existing miptree.
- *
- * Clobbers the current renderbuffer binding (ctx->CurrentRenderbuffer).
- */
-struct gl_renderbuffer *
-brw_get_rb_for_slice(struct brw_context *brw,
-                     struct intel_mipmap_tree *mt,
-                     unsigned level, unsigned layer, bool flat)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct gl_renderbuffer *rb = ctx->Driver.NewRenderbuffer(ctx, 0xDEADBEEF);
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-
-   rb->RefCount = 1;
-   rb->Format = mt->format;
-   rb->_BaseFormat = _mesa_get_format_base_format(mt->format);
-
-   /* Program takes care of msaa and mip-level access manually for stencil.
-    * The surface is also treated as Y-tiled instead of as W-tiled calling for
-    * twice the width and half the height in dimensions.
-    */
-   if (flat) {
-      const unsigned halign_stencil = 8;
-
-      rb->NumSamples = 0;
-      rb->Width = ALIGN(mt->total_width, halign_stencil) * 2;
-      rb->Height = (mt->total_height / mt->physical_depth0) / 2;
-      irb->mt_level = 0;
-   } else {
-      rb->NumSamples = mt->num_samples;
-      rb->Width = mt->logical_width0;
-      rb->Height = mt->logical_height0;
-      irb->mt_level = level;
-   }
-
-   irb->mt_layer = layer;
-
-   intel_miptree_reference(&irb->mt, mt);
-
-   return rb;
-}
-
-/**
  * Implementation of up or downsampling for window-system MSAA miptrees.
  */
 void
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index b250d8a8146..ac4f6154dc7 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -21,6 +21,8 @@
  * IN THE SOFTWARE.
  */
 
+#include "brw_context.h"
+#include "intel_fbo.h"
 #include "brw_meta_util.h"
 #include "main/fbobject.h"
 
@@ -259,3 +261,47 @@ brw_meta_mirror_clip_and_scissor(const struct gl_context *ctx,
 
    return false;
 }
+
+/**
+ * Creates a new named renderbuffer that wraps the first slice
+ * of an existing miptree.
+ *
+ * Clobbers the current renderbuffer binding (ctx->CurrentRenderbuffer).
+ */
+struct gl_renderbuffer *
+brw_get_rb_for_slice(struct brw_context *brw,
+                     struct intel_mipmap_tree *mt,
+                     unsigned level, unsigned layer, bool flat)
+{
+   struct gl_context *ctx = &brw->ctx;
+   struct gl_renderbuffer *rb = ctx->Driver.NewRenderbuffer(ctx, 0xDEADBEEF);
+   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+   rb->RefCount = 1;
+   rb->Format = mt->format;
+   rb->_BaseFormat = _mesa_get_format_base_format(mt->format);
+
+   /* Program takes care of msaa and mip-level access manually for stencil.
+    * The surface is also treated as Y-tiled instead of as W-tiled calling for
+    * twice the width and half the height in dimensions.
+    */
+   if (flat) {
+      const unsigned halign_stencil = 8;
+
+      rb->NumSamples = 0;
+      rb->Width = ALIGN(mt->total_width, halign_stencil) * 2;
+      rb->Height = (mt->total_height / mt->physical_depth0) / 2;
+      irb->mt_level = 0;
+   } else {
+      rb->NumSamples = mt->num_samples;
+      rb->Width = mt->logical_width0;
+      rb->Height = mt->logical_height0;
+      irb->mt_level = level;
+   }
+
+   irb->mt_layer = layer;
+
+   intel_miptree_reference(&irb->mt, mt);
+
+   return rb;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h b/src/mesa/drivers/dri/i965/brw_meta_util.h
index ac051e2b721..0929497b186 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -70,6 +70,11 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
                                    const struct intel_mipmap_tree *mt,
                                    const union gl_color_union *color);
 
+struct gl_renderbuffer *brw_get_rb_for_slice(struct brw_context *brw,
+                                             struct intel_mipmap_tree *mt,
+                                             unsigned level, unsigned layer,
+                                             bool flat);
+
 #ifdef __cplusplus
 }
 #endif