diff options
| author | Kenneth Graunke <[email protected]> | 2017-07-31 22:04:25 -0700 |
|---|---|---|
| committer | Andres Gomez <[email protected]> | 2017-08-19 13:46:04 +0300 |
| commit | 9e164c6aa9c7799e1cbd9a9b5f160f8ba505d6bd (patch) | |
| tree | 0a527dd0b78e573245f31c34b267082cf621fec1 /src | |
| parent | 7056362f8dfe2629c901de0b35315aa3aee0aec0 (diff) | |
i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.
Cc: [email protected]
Reviewed-by: Chris Wilson <[email protected]>
(cherry picked from commit 595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <[email protected]>
Conflicts:
src/mesa/drivers/dri/i965/intel_blit.c
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index b1e1eaa23ac..d6450b06739 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -188,7 +188,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw, * The offsets we get from ISL in the tiled case are already aligned. * In the linear case, we need to do some of our own aligning. */ - assert(mt->pitch % 64 == 0); uint32_t delta = *base_address_offset & 63; assert(delta % mt->cpp == 0); *base_address_offset -= delta; |