diff options
| author | Boyuan Zhang <[email protected]> | 2019-03-05 16:51:37 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:12 -0400 |
| commit | 7a5c22d32a43cd3f26de1f81e78dd49b96c329c7 (patch) | |
| tree | 38606fd2e95d7e89cd07975925cc11ac6b3d4a30 /src | |
| parent | 0c279711576c7298cfac561789f03f5531e1e0f1 (diff) | |
radeon/vcn: add defines for vcn 2.0 jpeg
Add neccesary register defines for vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <[email protected]>
Acked-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_vcn_dec.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h b/src/gallium/drivers/radeon/radeon_vcn_dec.h index 0c6de46b5c7..3ba42f3b77c 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_dec.h +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.h @@ -167,6 +167,31 @@ #define mmUVD_SOFT_RESET 0x05a0 #define mmUVD_SOFT_RESET_BASE_IDX 1 +#define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f +#define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e +#define vcnipUVD_JRBC_IB_REF_DATA 0x408f +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1 +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0 +#define vcnipUVD_JPEG_RB_BASE 0x4001 +#define vcnipUVD_JPEG_RB_SIZE 0x4004 +#define vcnipUVD_JPEG_RB_WPTR 0x4002 +#define vcnipUVD_JPEG_PITCH 0x401f +#define vcnipUVD_JPEG_UV_PITCH 0x4020 +#define vcnipJPEG_DEC_ADDR_MODE 0x4027 +#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024 +#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025 +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3 +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2 +#define vcnipUVD_JPEG_INDEX 0x402c +#define vcnipUVD_JPEG_DATA 0x402d +#define vcnipUVD_JPEG_TIER_CNTL2 0x400f +#define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e +#define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c +#define vcnipUVD_JPEG_INT_EN 0x400a +#define vcnipUVD_JPEG_CNTL 0x4000 +#define vcnipUVD_JPEG_RB_RPTR 0x4003 +#define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d + #define UVD_BASE_INST0_SEG0 0x00007800 #define UVD_BASE_INST0_SEG1 0x00007E00 #define UVD_BASE_INST0_SEG2 0 |