diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-25 10:53:17 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-07-07 17:03:38 +0200 |
| commit | 6b9dbb28ef71c2278dc41b8e72b55914dee7a635 (patch) | |
| tree | 9daaf8c96bc8f199319de25d4dc1aa23d18319ec /src | |
| parent | 2435b571de564e8de43507b8e2a53121a6c08a06 (diff) | |
radv/gfx10: update DB_DFSM_CONTROL register
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 09b04235e8b..79d71d2259e 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2720,8 +2720,14 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs, radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0, pa_sc_binner_cntl_0); - radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL, - db_dfsm_control); + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL, + db_dfsm_control); + } else { + radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL, + db_dfsm_control); + } } |