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authorRob Clark <[email protected]>2016-04-22 18:39:10 -0400
committerRob Clark <[email protected]>2016-04-24 13:40:57 -0400
commit610837fb9831b5b1430b31cdc6e110edf3fe7d94 (patch)
tree6c9c3cd405f5a4918186029b91edf70992839145 /src
parentadf795432f788b33822d3a94b704be4ca536c8f1 (diff)
freedreno/ir3: fix small RA bug
Normally the offset in the group would be the same, but not always. For example, in a sam(w) which only writes the 4th component. Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_ra.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_ra.c b/src/gallium/drivers/freedreno/ir3/ir3_ra.c
index ed3030d722a..e0c3c8028df 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_ra.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_ra.c
@@ -469,7 +469,8 @@ get_definer(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr,
*sz = MAX2(*sz, dsz);
- /* Fanout's are grouped, so *off should already valid */
+ debug_assert(instr->opc == OPC_META_FO);
+ *off = MAX2(*off, instr->fo.off);
d = dd;
}