diff options
| author | Samuel Pitoiset <[email protected]> | 2018-09-10 18:14:41 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-09-11 11:30:19 +0200 |
| commit | 3d08631fe5779cfadfeba3df89fbbddf3fde331b (patch) | |
| tree | 31fccd2751c2f3925826a59ffc4b7e88fdc30fd4 /src | |
| parent | 47e01e77d8b658606527f048cda786440f7fbe85 (diff) | |
radv: adjust ESGS ring buffer size computation on VI+
Noticed while working in this area. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 1741d5e9047..ae269c32c49 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1575,7 +1575,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta unsigned num_se = device->physical_device->rad_info.max_se; unsigned wave_size = 64; unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ - unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */ + /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16. + * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). + */ + unsigned gs_vertex_reuse = + (device->physical_device->rad_info.chip_class >= VI ? 32 : 16) * num_se; unsigned alignment = 256 * num_se; /* The maximum size is 63.999 MB per SE. */ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; |