diff options
| author | Kenneth Graunke <[email protected]> | 2012-12-15 01:14:03 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-12-02 13:25:11 -0800 |
| commit | 1110ba4c088e41548090d52d669157c3e9f6f9fa (patch) | |
| tree | 6425538e47f476e96af7a8c50a6169704caa7178 /src | |
| parent | 93658054c03b4463d301be83b20c8933e49a5771 (diff) | |
i965: Set vertical alignment unit to 4 on Broadwell.
Broadwell doesn't support a surface vertical alignment of 2. It only
supports VALIGN_4, VALIGN_8, or VALIGN_16. I chose 4 since it's the
least wasteful.
v2: Replace my comment with a better one from Eric. Move Broadwell
checks earlier so it's more obvious that "return 2" won't be hit.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 2c81eed741f..16af19f0090 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -117,6 +117,12 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw, if (format == MESA_FORMAT_S8) return brw->gen >= 7 ? 8 : 4; + /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4 + * should always be used, except for stencil buffers, which should be 8. + */ + if (brw->gen >= 8) + return 4; + if (multisampled) return 4; |