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authorJason Ekstrand <[email protected]>2019-04-01 21:23:01 -0500
committerKarol Herbst <[email protected]>2019-04-07 15:13:36 +0200
commit10a2fdacfa3f96a57fec304cf54d1c298e4f0943 (patch)
tree55c05981690dbab37348ede7fa47f96d80118090 /src
parent5450f1c9fb098ad85affb4fba9364052482e7016 (diff)
vc4: Prefer nir_src_comp_as_uint over nir_src_as_const_value
Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/vc4/vc4_nir_lower_io.c3
-rw-r--r--src/gallium/drivers/vc4/vc4_program.c31
2 files changed, 16 insertions, 18 deletions
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_io.c b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
index fc2baee1b9a..27051ec4030 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_io.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
@@ -180,8 +180,7 @@ vc4_nir_lower_vertex_attr(struct vc4_compile *c, nir_builder *b,
/* We only accept direct outputs and TGSI only ever gives them to us
* with an offset value of 0.
*/
- assert(nir_src_as_const_value(intr->src[0]) &&
- nir_src_as_const_value(intr->src[0])->u32[0] == 0);
+ assert(nir_src_as_uint(intr->src[0]) == 0);
/* Generate dword loads for the VPM values (Since these intrinsics may
* be reordered, the actual reads will be generated at the top of the
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index eb8b3a2c377..b57a6b3daf2 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -147,9 +147,8 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
static struct qreg
vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
{
- nir_const_value *buffer_index =
- nir_src_as_const_value(intr->src[0]);
- assert(buffer_index->u32[0] == 1);
+ unsigned buffer_index = nir_src_as_uint(intr->src[0]);
+ assert(buffer_index == 1);
assert(c->stage == QSTAGE_FRAG);
struct qreg offset = ntq_get_src(c, intr->src[1], 0);
@@ -161,7 +160,7 @@ vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
offset,
- qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index->u32[0]));
+ qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index));
c->num_texture_samples++;
@@ -1758,7 +1757,7 @@ ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
static void
ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
{
- assert(nir_src_as_const_value(instr->src[0])->u32[0] == 0);
+ assert(nir_src_as_uint(instr->src[0]) == 0);
/* Reads of the per-sample color need to be done in
* order.
@@ -1779,9 +1778,8 @@ static void
ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
{
assert(instr->num_components == 1);
-
- nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
- assert(const_offset && "vc4 doesn't support indirect inputs");
+ assert(nir_src_is_const(instr->src[0]) &&
+ "vc4 doesn't support indirect inputs");
if (c->stage == QSTAGE_FRAG &&
nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
@@ -1789,7 +1787,8 @@ ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
return;
}
- uint32_t offset = nir_intrinsic_base(instr) + const_offset->u32[0];
+ uint32_t offset = nir_intrinsic_base(instr) +
+ nir_src_as_uint(instr->src[0]);
int comp = nir_intrinsic_component(instr);
ntq_store_dest(c, &instr->dest, 0,
qir_MOV(c, c->inputs[offset * 4 + comp]));
@@ -1798,15 +1797,14 @@ ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
static void
ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
{
- nir_const_value *const_offset;
unsigned offset;
switch (instr->intrinsic) {
case nir_intrinsic_load_uniform:
assert(instr->num_components == 1);
- const_offset = nir_src_as_const_value(instr->src[0]);
- if (const_offset) {
- offset = nir_intrinsic_base(instr) + const_offset->u32[0];
+ if (nir_src_is_const(instr->src[0])) {
+ offset = nir_intrinsic_base(instr) +
+ nir_src_as_uint(instr->src[0]);
assert(offset % 4 == 0);
/* We need dwords */
offset = offset / 4;
@@ -1881,9 +1879,10 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
break;
case nir_intrinsic_store_output:
- const_offset = nir_src_as_const_value(instr->src[1]);
- assert(const_offset && "vc4 doesn't support indirect outputs");
- offset = nir_intrinsic_base(instr) + const_offset->u32[0];
+ assert(nir_src_is_const(instr->src[1]) &&
+ "vc4 doesn't support indirect outputs");
+ offset = nir_intrinsic_base(instr) +
+ nir_src_as_uint(instr->src[1]);
/* MSAA color outputs are the only case where we have an
* output that's not lowered to being a store of a single 32