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authorJason Ekstrand <[email protected]>2017-06-21 19:25:16 -0700
committerJason Ekstrand <[email protected]>2017-07-22 20:59:22 -0700
commit06ef36d319bbce22ce70a8ae426b07a4dede9f21 (patch)
treef7067fcf9a244c588d9d66ed6345fcd709763b86 /src
parent268ba028dcbdaea25a972a460c1636f485d5c5bc (diff)
i965/miptree: Use ISL_AUX_STATE_PARTIAL_CLEAR for CCS_D
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0d1e093276d..ee99571a22c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1928,7 +1928,7 @@ get_ccs_d_resolve_op(enum isl_aux_state aux_state,
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
- case ISL_AUX_STATE_COMPRESSED_CLEAR:
+ case ISL_AUX_STATE_PARTIAL_CLEAR:
if (!ccs_supported)
return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
else
@@ -1937,9 +1937,9 @@ get_ccs_d_resolve_op(enum isl_aux_state aux_state,
case ISL_AUX_STATE_PASS_THROUGH:
return BLORP_FAST_CLEAR_OP_NONE;
- case ISL_AUX_STATE_PARTIAL_CLEAR:
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_AUX_INVALID:
+ case ISL_AUX_STATE_COMPRESSED_CLEAR:
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
break;
}
@@ -2074,10 +2074,10 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
case ISL_AUX_STATE_CLEAR:
assert(aux_usage == ISL_AUX_USAGE_CCS_D);
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_CLEAR);
+ ISL_AUX_STATE_PARTIAL_CLEAR);
break;
- case ISL_AUX_STATE_COMPRESSED_CLEAR:
+ case ISL_AUX_STATE_PARTIAL_CLEAR:
assert(aux_usage == ISL_AUX_USAGE_CCS_D);
break; /* Nothing to do */
@@ -2085,7 +2085,7 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
/* Nothing to do */
break;
- case ISL_AUX_STATE_PARTIAL_CLEAR:
+ case ISL_AUX_STATE_COMPRESSED_CLEAR:
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_AUX_INVALID: