diff options
| author | Dave Airlie <[email protected]> | 2017-12-29 11:00:34 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-12-29 11:43:30 +1000 |
| commit | 868377ab33e09a211ddc9f0ca82b15e7b40dd95b (patch) | |
| tree | 32cbd61e31ddb35bc1f9bb5d49bdee1e30628947 /src | |
| parent | 59515780433837ad3975f8ed20b93cf2fe6870e5 (diff) | |
radv/gfx9: use a bigger hammer to flush cb/db caches.
amdvlk is probably more subtle than this but it never uses
the inv cb/db variants, we fail some CTS tests without this.
Fixes:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
Fixes: c2fbeb7ca05 (radv: add GFX9 cache flushing support.)
Reviewed-by: Bas Nieuwenhuizen <[email protected]> (for now :-)
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 972d37948aa..a6981c136e7 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -991,6 +991,11 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, if (chip_class >= GFX9 && flush_cb_db) { unsigned cb_db_event, tc_flags; +#if 0 + /* This breaks a bunch of: + dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*. + use the big hammer always. + */ /* Set the CB/DB flush event. */ switch (flush_cb_db) { case RADV_CMD_FLAG_FLUSH_AND_INV_CB: @@ -1003,7 +1008,9 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, /* both CB & DB */ cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; } - +#else + cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; +#endif /* TC | TC_WB = invalidate L2 data * TC_MD | TC_WB = invalidate L2 metadata * TC | TC_WB | TC_MD = invalidate L2 data & metadata |