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authorDave Airlie <[email protected]>2017-05-06 21:14:11 +0100
committerEmil Velikov <[email protected]>2017-05-08 11:37:10 +0100
commit3db01cd4e7eac377a991c2a5c63adbdf846cb5bf (patch)
tree93f2a1c96090fad3dbcc89b1ae2f67cd1a9ccb61 /src
parent396f9ae52f9622e564a7c0912277411d4228292f (diff)
radv: apply the tess+GS hang workaround to Polaris12 as well
As I pointed out for radeonsi, and AMD confirmed, so fix this in radv as well. Cc: "17.1" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 2add79a73291e40621081b9a12938ac1931b9e96)
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/si_cmd_buffer.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index fbb21117aa3..8d7db96445c 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -672,7 +672,8 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
if (family == CHIP_TONGA ||
family == CHIP_FIJI ||
family == CHIP_POLARIS10 ||
- family == CHIP_POLARIS11)
+ family == CHIP_POLARIS11 ||
+ family == CHIP_POLARIS12)
partial_vs_wave = true;
} else {
partial_vs_wave = true;