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authorAnuj Phogat <[email protected]>2017-05-11 15:57:46 -0700
committerAnuj Phogat <[email protected]>2017-06-09 16:02:59 -0700
commit30e749c8f1cae530fbb7d24e1c5e7097f7cd1821 (patch)
tree776f5b186358a20e4ad6a423e20b78ed8aa1cd21 /src
parent56b4d82729a045d8e06953a96bb4da2aa813d198 (diff)
i965/cnl: Update few assertions
Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_compiler.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 95cbfb7c33e..78873744ce5 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1156,7 +1156,7 @@ brw_stage_has_packed_dispatch(const struct gen_device_info *devinfo,
* to do a full test run with brw_fs_test_dispatch_packing() hooked up to
* the NIR front-end before changing this assertion.
*/
- assert(devinfo->gen <= 9);
+ assert(devinfo->gen <= 10);
switch (stage) {
case MESA_SHADER_FRAGMENT: {
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index bff3475b3d9..94d8d8b978a 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -290,7 +290,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
- assert(brw->gen >= 7 && brw->gen <= 9);
+ assert(brw->gen >= 7 && brw->gen <= 10);
if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
GL_ELEMENT_ARRAY_BARRIER_BIT |