diff options
| author | Tom Stellard <[email protected]> | 2012-08-20 21:08:03 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-21 15:42:44 +0000 |
| commit | 05882985757e655f5298af483c881008d45e6249 (patch) | |
| tree | ac1ed3f0b9ff0f55f23e34fb7a2d0e5596f707a9 /src | |
| parent | 1a25ebe3ce95a6a4aef7c844dbe95909976b68da (diff) | |
radeon/llvm: Add helper function for getting sub reg indices
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/R600InstrInfo.cpp | 9 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600RegisterInfo.cpp | 12 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600RegisterInfo.h | 4 |
3 files changed, 19 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp index 7a8a58e7cfe..12b46654bb7 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.cpp +++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp @@ -50,16 +50,13 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - - unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y, - AMDGPU::sel_z, AMDGPU::sel_w}; - if (AMDGPU::R600_Reg128RegClass.contains(DestReg) && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) { for (unsigned i = 0; i < 4; i++) { + unsigned SubRegIndex = RI.getSubRegFromChannel(i); BuildMI(MBB, MI, DL, get(AMDGPU::MOV)) - .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define) - .addReg(RI.getSubReg(SrcReg, subRegMap[i])) + .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) + .addReg(RI.getSubReg(SrcReg, SubRegIndex)) .addReg(0) // PREDICATE_BIT .addReg(DestReg, RegState::Define | RegState::Implicit); } diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.cpp b/src/gallium/drivers/radeon/R600RegisterInfo.cpp index 94752410bfb..c2e40c7214a 100644 --- a/src/gallium/drivers/radeon/R600RegisterInfo.cpp +++ b/src/gallium/drivers/radeon/R600RegisterInfo.cpp @@ -112,4 +112,16 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( case MVT::i32: return AMDGPU::R600_TReg32RegisterClass; } } + +unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const +{ + switch (Channel) { + default: assert(!"Invalid channel index"); return 0; + case 0: return AMDGPU::sel_x; + case 1: return AMDGPU::sel_y; + case 2: return AMDGPU::sel_z; + case 3: return AMDGPU::sel_w; + } +} + #include "R600HwRegInfo.include" diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.h b/src/gallium/drivers/radeon/R600RegisterInfo.h index f45995d7d8b..60f6d53b2d8 100644 --- a/src/gallium/drivers/radeon/R600RegisterInfo.h +++ b/src/gallium/drivers/radeon/R600RegisterInfo.h @@ -46,6 +46,10 @@ struct R600RegisterInfo : public AMDGPURegisterInfo /// type to use in the CFGStructurizer virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; + /// getSubRegFromChannel - Return the sub reg enum value for the given + /// Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x) + unsigned getSubRegFromChannel(unsigned Channel) const; + private: /// getHWRegIndexGen - Generated function returns a register's encoding unsigned getHWRegIndexGen(unsigned reg) const; |