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authorEric Anholt <[email protected]>2012-10-09 15:31:42 -0700
committerEric Anholt <[email protected]>2012-10-15 11:53:23 -0700
commitbcfd51f8c45be2ee99f302ed3310c34998b19ff6 (patch)
tree147b3daf47e3020e363a4787ab4a163e3e0e3884 /src
parent422566e1c7bb4b14fdc133a963bd9787cd98f369 (diff)
mesa: Remove Mesa IR opcodes that existed only for NV_vertex_program.
v2: Remove dead positive() function, caught by Matt. Reviewed-by: Brian Paul <[email protected]> (v1)
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c1
-rw-r--r--src/mesa/program/prog_execute.c61
-rw-r--r--src/mesa/program/prog_instruction.c7
-rw-r--r--src/mesa/program/prog_instruction.h7
-rw-r--r--src/mesa/program/prog_optimize.c2
-rw-r--r--src/mesa/program/prog_print.c7
6 files changed, 0 insertions, 85 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 7a6e0673678..3038d84f3ed 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1088,7 +1088,6 @@ upload_program(struct i915_fragment_program *p)
case OPCODE_BGNLOOP:
case OPCODE_BGNSUB:
- case OPCODE_BRA:
case OPCODE_BRK:
case OPCODE_CAL:
case OPCODE_CONT:
diff --git a/src/mesa/program/prog_execute.c b/src/mesa/program/prog_execute.c
index dd1706e1444..f57027c0756 100644
--- a/src/mesa/program/prog_execute.c
+++ b/src/mesa/program/prog_execute.c
@@ -79,23 +79,6 @@
static const GLfloat ZeroVec[4] = { 0.0F, 0.0F, 0.0F, 0.0F };
-
-/**
- * Return TRUE for +0 and other positive values, FALSE otherwise.
- * Used for RCC opcode.
- */
-static inline GLboolean
-positive(float x)
-{
- fi_type fi;
- fi.f = x;
- if (fi.i & 0x80000000)
- return GL_FALSE;
- return GL_TRUE;
-}
-
-
-
/**
* Return a pointer to the 4-element float vector specified by the given
* source register.
@@ -728,13 +711,6 @@ _mesa_execute_program(struct gl_context * ctx,
break;
case OPCODE_ENDSUB: /* end subroutine */
break;
- case OPCODE_BRA: /* branch (conditional) */
- if (eval_condition(machine, inst)) {
- /* take branch */
- /* Subtract 1 here since we'll do pc++ below */
- pc = inst->BranchTarget - 1;
- }
- break;
case OPCODE_BRK: /* break out of loop (conditional) */
ASSERT(program->Instructions[inst->BranchTarget].Opcode
== OPCODE_ENDLOOP);
@@ -1367,43 +1343,6 @@ _mesa_execute_program(struct gl_context * ctx,
store_vector4(inst, machine, result);
}
break;
- case OPCODE_RCC: /* clamped riciprocal */
- {
- const float largest = 1.884467e+19, smallest = 5.42101e-20;
- GLfloat a[4], r, result[4];
- fetch_vector1(&inst->SrcReg[0], machine, a);
- if (DEBUG_PROG) {
- if (a[0] == 0)
- printf("RCC(0)\n");
- else if (IS_INF_OR_NAN(a[0]))
- printf("RCC(inf)\n");
- }
- if (a[0] == 1.0F) {
- r = 1.0F;
- }
- else {
- r = 1.0F / a[0];
- }
- if (positive(r)) {
- if (r > largest) {
- r = largest;
- }
- else if (r < smallest) {
- r = smallest;
- }
- }
- else {
- if (r < -largest) {
- r = -largest;
- }
- else if (r > -smallest) {
- r = -smallest;
- }
- }
- result[0] = result[1] = result[2] = result[3] = r;
- store_vector4(inst, machine, result);
- }
- break;
case OPCODE_RCP:
{
diff --git a/src/mesa/program/prog_instruction.c b/src/mesa/program/prog_instruction.c
index d69d7b2d465..0bd45b09bab 100644
--- a/src/mesa/program/prog_instruction.c
+++ b/src/mesa/program/prog_instruction.c
@@ -154,13 +154,9 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
{ OPCODE_ABS, "ABS", 1, 1 },
{ OPCODE_ADD, "ADD", 2, 1 },
{ OPCODE_AND, "AND", 2, 1 },
- { OPCODE_ARA, "ARA", 1, 1 },
{ OPCODE_ARL, "ARL", 1, 1 },
- { OPCODE_ARL_NV, "ARL_NV", 1, 1 },
- { OPCODE_ARR, "ARL", 1, 1 },
{ OPCODE_BGNLOOP,"BGNLOOP", 0, 0 },
{ OPCODE_BGNSUB, "BGNSUB", 0, 0 },
- { OPCODE_BRA, "BRA", 0, 0 },
{ OPCODE_BRK, "BRK", 0, 0 },
{ OPCODE_CAL, "CAL", 0, 0 },
{ OPCODE_CMP, "CMP", 3, 1 },
@@ -210,10 +206,7 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
{ OPCODE_PK4B, "PK4B", 1, 1 },
{ OPCODE_PK4UB, "PK4UB", 1, 1 },
{ OPCODE_POW, "POW", 2, 1 },
- { OPCODE_POPA, "POPA", 0, 0 },
{ OPCODE_PRINT, "PRINT", 1, 0 },
- { OPCODE_PUSHA, "PUSHA", 0, 0 },
- { OPCODE_RCC, "RCC", 1, 1 },
{ OPCODE_RCP, "RCP", 1, 1 },
{ OPCODE_RET, "RET", 0, 0 },
{ OPCODE_RFL, "RFL", 1, 1 },
diff --git a/src/mesa/program/prog_instruction.h b/src/mesa/program/prog_instruction.h
index 656556dd4ee..7c09cdabf0f 100644
--- a/src/mesa/program/prog_instruction.h
+++ b/src/mesa/program/prog_instruction.h
@@ -148,13 +148,9 @@ typedef enum prog_opcode {
OPCODE_ABS, /* X X 1.1 X */
OPCODE_ADD, /* X X X X X */
OPCODE_AND, /* */
- OPCODE_ARA, /* 2 */
OPCODE_ARL, /* X X X */
- OPCODE_ARL_NV, /* 2 */
- OPCODE_ARR, /* 2 */
OPCODE_BGNLOOP, /* opt */
OPCODE_BGNSUB, /* opt */
- OPCODE_BRA, /* 2 */
OPCODE_BRK, /* 2 opt */
OPCODE_CAL, /* 2 2 opt */
OPCODE_CMP, /* X X */
@@ -204,10 +200,7 @@ typedef enum prog_opcode {
OPCODE_PK4B, /* X */
OPCODE_PK4UB, /* X */
OPCODE_POW, /* X X X X */
- OPCODE_POPA, /* 3 */
OPCODE_PRINT, /* X X */
- OPCODE_PUSHA, /* 3 */
- OPCODE_RCC, /* 1.1 */
OPCODE_RCP, /* X X X X X */
OPCODE_RET, /* 2 2 opt */
OPCODE_RFL, /* X */
diff --git a/src/mesa/program/prog_optimize.c b/src/mesa/program/prog_optimize.c
index e89e8d6a45c..78d09f1cbe1 100644
--- a/src/mesa/program/prog_optimize.c
+++ b/src/mesa/program/prog_optimize.c
@@ -392,7 +392,6 @@ find_next_use(const struct gl_program *prog,
switch (inst->Opcode) {
case OPCODE_BGNLOOP:
case OPCODE_BGNSUB:
- case OPCODE_BRA:
case OPCODE_CAL:
case OPCODE_CONT:
case OPCODE_IF:
@@ -439,7 +438,6 @@ _mesa_is_flow_control_opcode(enum prog_opcode opcode)
switch (opcode) {
case OPCODE_BGNLOOP:
case OPCODE_BGNSUB:
- case OPCODE_BRA:
case OPCODE_CAL:
case OPCODE_CONT:
case OPCODE_IF:
diff --git a/src/mesa/program/prog_print.c b/src/mesa/program/prog_print.c
index bc5dc580367..a560b53537f 100644
--- a/src/mesa/program/prog_print.c
+++ b/src/mesa/program/prog_print.c
@@ -748,13 +748,6 @@ _mesa_fprint_instruction_opt(FILE *f,
fprint_src_reg(f, &inst->SrcReg[0], mode, prog);
fprint_comment(f, inst);
break;
- case OPCODE_BRA:
- fprintf(f, "BRA %d (%s%s)",
- inst->BranchTarget,
- _mesa_condcode_string(inst->DstReg.CondMask),
- _mesa_swizzle_string(inst->DstReg.CondSwizzle, 0, GL_FALSE));
- fprint_comment(f, inst);
- break;
case OPCODE_IF:
if (inst->SrcReg[0].File != PROGRAM_UNDEFINED) {
/* Use ordinary register */