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authorRob Clark <[email protected]>2016-03-21 19:55:37 -0400
committerRob Clark <[email protected]>2016-03-28 10:19:53 -0400
commitb4c72b792caecd8be271af20de92d24b4ae7da4c (patch)
tree93300e7809d46cf964a1d0d37bcf8b40083222db /src
parent3ca034cada87aea58a92113cb38cf92a97d70c55 (diff)
freedreno/ir3: fix for load_front_face intrinsic
Seems like trying to widen in the same instruction as the add.s does a non-sign-extending widen. Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 88f6e168558..3d656d4a34d 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -1258,7 +1258,14 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
ctx->frag_face = create_input(b, 0);
ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
}
- dst[0] = ir3_ADD_S(b, ctx->frag_face, 0, create_immed(b, 1), 0);
+ /* for fragface, we always get -1 or 0, but that is inverse
+ * of what nir expects (where ~0 is true). Unfortunately
+ * trying to widen from half to full in add.s seems to do a
+ * non-sign-extending widen (resulting in something that
+ * gets interpreted as float Inf??)
+ */
+ dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
+ dst[0] = ir3_ADD_S(b, dst[0], 0, create_immed(b, 1), 0);
break;
case nir_intrinsic_discard_if:
case nir_intrinsic_discard: {