diff options
| author | Kenneth Graunke <[email protected]> | 2018-06-04 03:09:59 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2018-06-04 09:43:09 -0700 |
| commit | b3ba47c5926b3a5850403b1ab0df37815a203d9d (patch) | |
| tree | 2add50bf8f7650ab1cea3b9df0834e00f1eae45b /src | |
| parent | 06d3c65098097675a34035da3043a71061fad17b (diff) | |
i965: Fix batch-last mode to properly swap BOs.
On pre-4.13 kernels, which don't support I915_EXEC_BATCH_FIRST, we move
the validation list entry to the end...but incorrectly left the exec_bo
array alone, causing a mismatch where exec_bos[0] no longer corresponded
with validation_list[0] (and similarly for the last entry).
One example of resulting breakage is that we'd update bo->gtt_offset
based on the wrong buffer. This wreaked total havoc when trying to use
softpin, and likely caused unnecessary relocations in the normal case.
Fixes: 29ba502a4e28471f67e4e904ae503157087efd20 (i965: Use I915_EXEC_BATCH_FIRST when available.)
Reviewed-by: Chris Wilson <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 8f47e613df8..f51edf92346 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -780,11 +780,16 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) } else { /* Move the batch to the end of the validation list */ struct drm_i915_gem_exec_object2 tmp; + struct brw_bo *tmp_bo; const unsigned index = batch->exec_count - 1; tmp = *entry; *entry = batch->validation_list[index]; batch->validation_list[index] = tmp; + + tmp_bo = batch->exec_bos[0]; + batch->exec_bos[0] = batch->exec_bos[index]; + batch->exec_bos[index] = tmp_bo; } ret = execbuffer(dri_screen->fd, batch, brw->hw_ctx, |