diff options
| author | Paul Berry <[email protected]> | 2013-02-23 07:22:01 -0800 |
|---|---|---|
| committer | Paul Berry <[email protected]> | 2013-03-15 09:24:54 -0700 |
| commit | 36b252e94724b2512ea941eff2b3a3abeb80be79 (patch) | |
| tree | 3f904073b430eed86b128b73e6142fbc4ad458b2 /src | |
| parent | 9e729a79b0d5c7f2bf42262d57f6e0994c625dbe (diff) | |
Replace gl_vert_result enum with gl_varying_slot.
This patch makes the following search-and-replace changes:
gl_vert_result -> gl_varying_slot
VERT_RESULT_* -> VARYING_SLOT_*
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Tested-by: Brian Paul <[email protected]>
Diffstat (limited to 'src')
45 files changed, 358 insertions, 391 deletions
diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp index 53c4c51cd14..531effd6a32 100644 --- a/src/glsl/builtin_variables.cpp +++ b/src/glsl/builtin_variables.cpp @@ -47,8 +47,8 @@ struct builtin_variable { }; static const builtin_variable builtin_core_vs_variables[] = { - { ir_var_shader_out, VERT_RESULT_HPOS, "vec4", "gl_Position" }, - { ir_var_shader_out, VERT_RESULT_PSIZ, "float", "gl_PointSize" }, + { ir_var_shader_out, VARYING_SLOT_POS, "vec4", "gl_Position" }, + { ir_var_shader_out, VARYING_SLOT_PSIZ, "float", "gl_PointSize" }, }; static const builtin_variable builtin_core_fs_variables[] = { @@ -96,12 +96,12 @@ static const builtin_variable builtin_110_deprecated_vs_variables[] = { { ir_var_shader_in, VERT_ATTRIB_TEX6, "vec4", "gl_MultiTexCoord6" }, { ir_var_shader_in, VERT_ATTRIB_TEX7, "vec4", "gl_MultiTexCoord7" }, { ir_var_shader_in, VERT_ATTRIB_FOG, "float", "gl_FogCoord" }, - { ir_var_shader_out, VERT_RESULT_CLIP_VERTEX, "vec4", "gl_ClipVertex" }, - { ir_var_shader_out, VERT_RESULT_COL0, "vec4", "gl_FrontColor" }, - { ir_var_shader_out, VERT_RESULT_BFC0, "vec4", "gl_BackColor" }, - { ir_var_shader_out, VERT_RESULT_COL1, "vec4", "gl_FrontSecondaryColor" }, - { ir_var_shader_out, VERT_RESULT_BFC1, "vec4", "gl_BackSecondaryColor" }, - { ir_var_shader_out, VERT_RESULT_FOGC, "float", "gl_FogFragCoord" }, + { ir_var_shader_out, VARYING_SLOT_CLIP_VERTEX, "vec4", "gl_ClipVertex" }, + { ir_var_shader_out, VARYING_SLOT_COL0, "vec4", "gl_FrontColor" }, + { ir_var_shader_out, VARYING_SLOT_BFC0, "vec4", "gl_BackColor" }, + { ir_var_shader_out, VARYING_SLOT_COL1, "vec4", "gl_FrontSecondaryColor" }, + { ir_var_shader_out, VARYING_SLOT_BFC1, "vec4", "gl_BackSecondaryColor" }, + { ir_var_shader_out, VARYING_SLOT_FOGC, "float", "gl_FogFragCoord" }, }; static const builtin_variable builtin_120_fs_variables[] = { @@ -755,7 +755,7 @@ generate_110_vs_variables(exec_list *instructions, add_variable(instructions, state->symbols, "gl_TexCoord", vec4_array_type, ir_var_shader_out, - VERT_RESULT_TEX0); + VARYING_SLOT_TEX0); generate_ARB_draw_buffers_variables(instructions, state, false, vertex_shader); @@ -816,7 +816,7 @@ generate_130_vs_variables(exec_list *instructions, add_variable(instructions, state->symbols, "gl_ClipDistance", clip_distance_array_type, ir_var_shader_out, - VERT_RESULT_CLIP_DIST0); + VARYING_SLOT_CLIP_DIST0); } diff --git a/src/glsl/ir.h b/src/glsl/ir.h index 393b4867368..4d9e8a7ee0b 100644 --- a/src/glsl/ir.h +++ b/src/glsl/ir.h @@ -505,7 +505,7 @@ public: * The precise meaning of this field depends on the nature of the variable. * * - Vertex shader input: one of the values from \c gl_vert_attrib. - * - Vertex shader output: one of the values from \c gl_vert_result. + * - Vertex shader output: one of the values from \c gl_varying_slot. * - Fragment shader input: one of the values from \c gl_frag_attrib. * - Fragment shader output: one of the values from \c gl_frag_result. * - Uniforms: Per-stage uniform slot number for default uniform block. diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp index 616933dfd3d..4da28e9854c 100644 --- a/src/glsl/link_varyings.cpp +++ b/src/glsl/link_varyings.cpp @@ -604,7 +604,7 @@ private: /** * The location which has been assigned for this varying. This is * expressed in multiples of a float, with the first generic varying - * (i.e. the one referred to by VERT_RESULT_VAR0 or FRAG_ATTRIB_VAR0) + * (i.e. the one referred to by VARYING_SLOT_VAR0 or FRAG_ATTRIB_VAR0) * represented by the value 0. */ unsigned generic_location; @@ -959,7 +959,7 @@ assign_varying_locations(struct gl_context *ctx, tfeedback_decl *tfeedback_decls) { /* FINISHME: Set dynamically when geometry shader support is added. */ - const unsigned producer_base = VERT_RESULT_VAR0; + const unsigned producer_base = VARYING_SLOT_VAR0; const unsigned consumer_base = FRAG_ATTRIB_VAR0; varying_matches matches(ctx->Const.DisableVaryingPacking); hash_table *tfeedback_candidates diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index 57e7a9ad369..adcfda8a9d2 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -1777,7 +1777,7 @@ link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) if (prog->_LinkedShaders[MESA_SHADER_VERTEX] != NULL) { link_invalidate_variable_locations( prog->_LinkedShaders[MESA_SHADER_VERTEX], - VERT_ATTRIB_GENERIC0, VERT_RESULT_VAR0); + VERT_ATTRIB_GENERIC0, VARYING_SLOT_VAR0); } /* FINISHME: Geometry shaders not implemented yet */ if (prog->_LinkedShaders[MESA_SHADER_FRAGMENT] != NULL) { diff --git a/src/glsl/lower_packed_varyings.cpp b/src/glsl/lower_packed_varyings.cpp index 8a40f5e72e5..b4cc5cd0d52 100644 --- a/src/glsl/lower_packed_varyings.cpp +++ b/src/glsl/lower_packed_varyings.cpp @@ -117,7 +117,7 @@ private: /** * Location representing the first generic varying slot for this shader - * stage (e.g. VERT_RESULT_VAR0 if we are packing vertex shader outputs). + * stage (e.g. VARYING_SLOT_VAR0 if we are packing vertex shader outputs). * Varyings whose location is less than this value are assumed to * correspond to special fixed function hardware, so they are not lowered. */ diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 6cf2bd293cf..bfb64baf321 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -134,7 +134,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) struct brw_indirect plane_ptr = brw_indirect(4, 0); struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD); GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_HPOS); + VARYING_SLOT_POS); brw_MOV(p, get_addr_reg(vtx0), brw_address(c->reg.vertex[0])); brw_MOV(p, get_addr_reg(vtx1), brw_address(c->reg.vertex[1])); diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index a29f8e05b34..548e7e9d067 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -233,7 +233,7 @@ void brw_clip_tri( struct brw_clip_compile *c ) struct brw_indirect outlist_ptr = brw_indirect(5, 0); struct brw_indirect freelist_ptr = brw_indirect(6, 0); GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_HPOS); + VARYING_SLOT_POS); brw_MOV(p, get_addr_reg(vtxPrev), brw_address(c->reg.vertex[2]) ); brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c)); @@ -485,7 +485,7 @@ static void brw_clip_test( struct brw_clip_compile *c ) struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */ GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_HPOS); + VARYING_SLOT_POS); brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0])); brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1])); diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c index 03c7d428bd2..e4f4835b23b 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c @@ -53,7 +53,7 @@ static void compute_tri_direction( struct brw_clip_compile *c ) struct brw_reg e = c->reg.tmp0; struct brw_reg f = c->reg.tmp1; GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_HPOS); + VARYING_SLOT_POS); struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset); struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset); struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset); @@ -130,10 +130,10 @@ static void copy_bfc( struct brw_clip_compile *c ) /* Do we have any colors to copy? */ - if (!(brw_clip_have_vert_result(c, VERT_RESULT_COL0) && - brw_clip_have_vert_result(c, VERT_RESULT_BFC0)) && - !(brw_clip_have_vert_result(c, VERT_RESULT_COL1) && - brw_clip_have_vert_result(c, VERT_RESULT_BFC1))) + if (!(brw_clip_have_vert_result(c, VARYING_SLOT_COL0) && + brw_clip_have_vert_result(c, VARYING_SLOT_BFC0)) && + !(brw_clip_have_vert_result(c, VARYING_SLOT_COL1) && + brw_clip_have_vert_result(c, VARYING_SLOT_BFC1))) return; /* In some wierd degnerate cases we can end up testing the @@ -156,25 +156,25 @@ static void copy_bfc( struct brw_clip_compile *c ) GLuint i; for (i = 0; i < 3; i++) { - if (brw_clip_have_vert_result(c, VERT_RESULT_COL0) && - brw_clip_have_vert_result(c, VERT_RESULT_BFC0)) + if (brw_clip_have_vert_result(c, VARYING_SLOT_COL0) && + brw_clip_have_vert_result(c, VARYING_SLOT_BFC0)) brw_MOV(p, byte_offset(c->reg.vertex[i], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_COL0)), + VARYING_SLOT_COL0)), byte_offset(c->reg.vertex[i], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_BFC0))); + VARYING_SLOT_BFC0))); - if (brw_clip_have_vert_result(c, VERT_RESULT_COL1) && - brw_clip_have_vert_result(c, VERT_RESULT_BFC1)) + if (brw_clip_have_vert_result(c, VARYING_SLOT_COL1) && + brw_clip_have_vert_result(c, VARYING_SLOT_BFC1)) brw_MOV(p, byte_offset(c->reg.vertex[i], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_COL1)), + VARYING_SLOT_COL1)), byte_offset(c->reg.vertex[i], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_BFC1))); + VARYING_SLOT_BFC1))); } } brw_ENDIF(p); @@ -235,7 +235,7 @@ static void merge_edgeflags( struct brw_clip_compile *c ) brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8)); brw_MOV(p, byte_offset(c->reg.vertex[0], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_EDGE)), + VARYING_SLOT_EDGE)), brw_imm_f(0)); brw_set_predicate_control(p, BRW_PREDICATE_NONE); @@ -243,7 +243,7 @@ static void merge_edgeflags( struct brw_clip_compile *c ) brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9)); brw_MOV(p, byte_offset(c->reg.vertex[2], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_EDGE)), + VARYING_SLOT_EDGE)), brw_imm_f(0)); brw_set_predicate_control(p, BRW_PREDICATE_NONE); } @@ -257,7 +257,7 @@ static void apply_one_offset( struct brw_clip_compile *c, { struct brw_compile *p = &c->func; GLuint ndc_offset = brw_vert_result_to_offset(&c->vue_map, - BRW_VERT_RESULT_NDC); + BRW_VARYING_SLOT_NDC); struct brw_reg z = deref_1f(vert, ndc_offset + 2 * type_sz(BRW_REGISTER_TYPE_F)); @@ -316,7 +316,7 @@ static void emit_lines(struct brw_clip_compile *c, brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, deref_1f(v0, brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_EDGE)), + VARYING_SLOT_EDGE)), brw_imm_f(0)); brw_IF(p, BRW_EXECUTE_1); { @@ -358,7 +358,7 @@ static void emit_points(struct brw_clip_compile *c, brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_NZ, deref_1f(v0, brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_EDGE)), + VARYING_SLOT_EDGE)), brw_imm_f(0)); brw_IF(p, BRW_EXECUTE_1); { @@ -473,7 +473,7 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c ) brw_clip_tri_init_vertices(c); brw_clip_init_ff_sync(c); - assert(brw_clip_have_vert_result(c, VERT_RESULT_EDGE)); + assert(brw_clip_have_vert_result(c, VARYING_SLOT_EDGE)); if (c->key.fill_ccw == CLIP_CULL && c->key.fill_cw == CLIP_CULL) { diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index bf8cc3ac815..4df2498a5b9 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -110,9 +110,9 @@ static void brw_clip_project_vertex( struct brw_clip_compile *c, struct brw_compile *p = &c->func; struct brw_reg tmp = get_tmp(c); GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_HPOS); + VARYING_SLOT_POS); GLuint ndc_offset = brw_vert_result_to_offset(&c->vue_map, - BRW_VERT_RESULT_NDC); + BRW_VARYING_SLOT_NDC); /* Fixup position. Extract from the original vertex and re-project * to screen space: @@ -155,20 +155,20 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, int vert_result = c->vue_map.slot_to_vert_result[slot]; GLuint delta = brw_vue_slot_to_offset(slot); - if (vert_result == VERT_RESULT_EDGE) { + if (vert_result == VARYING_SLOT_EDGE) { if (force_edgeflag) brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1)); else brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta)); - } else if (vert_result == VERT_RESULT_PSIZ || - vert_result == VERT_RESULT_CLIP_DIST0 || - vert_result == VERT_RESULT_CLIP_DIST1) { + } else if (vert_result == VARYING_SLOT_PSIZ || + vert_result == VARYING_SLOT_CLIP_DIST0 || + vert_result == VARYING_SLOT_CLIP_DIST1) { /* PSIZ doesn't need interpolation because it isn't used by the * fragment shader. CLIP_DIST0 and CLIP_DIST1 don't need * intepolation because on pre-GEN6, these are just placeholder VUE * slots that don't perform any action. */ - } else if (vert_result < VERT_RESULT_MAX) { + } else if (vert_result < VARYING_SLOT_MAX) { /* This is a true vertex result (and not a special value for the VUE * header), so interpolate: * @@ -299,41 +299,41 @@ void brw_clip_copy_colors( struct brw_clip_compile *c, { struct brw_compile *p = &c->func; - if (brw_clip_have_vert_result(c, VERT_RESULT_COL0)) + if (brw_clip_have_vert_result(c, VARYING_SLOT_COL0)) brw_MOV(p, byte_offset(c->reg.vertex[to], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_COL0)), + VARYING_SLOT_COL0)), byte_offset(c->reg.vertex[from], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_COL0))); + VARYING_SLOT_COL0))); - if (brw_clip_have_vert_result(c, VERT_RESULT_COL1)) + if (brw_clip_have_vert_result(c, VARYING_SLOT_COL1)) brw_MOV(p, byte_offset(c->reg.vertex[to], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_COL1)), + VARYING_SLOT_COL1)), byte_offset(c->reg.vertex[from], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_COL1))); + VARYING_SLOT_COL1))); - if (brw_clip_have_vert_result(c, VERT_RESULT_BFC0)) + if (brw_clip_have_vert_result(c, VARYING_SLOT_BFC0)) brw_MOV(p, byte_offset(c->reg.vertex[to], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_BFC0)), + VARYING_SLOT_BFC0)), byte_offset(c->reg.vertex[from], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_BFC0))); + VARYING_SLOT_BFC0))); - if (brw_clip_have_vert_result(c, VERT_RESULT_BFC1)) + if (brw_clip_have_vert_result(c, VARYING_SLOT_BFC1)) brw_MOV(p, byte_offset(c->reg.vertex[to], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_BFC1)), + VARYING_SLOT_BFC1)), byte_offset(c->reg.vertex[from], brw_vert_result_to_offset(&c->vue_map, - VERT_RESULT_BFC1))); + VARYING_SLOT_BFC1))); } diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index d80332c10b0..0f1d4519638 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -323,26 +323,26 @@ struct brw_wm_prog_data { /** * Enum representing the i965-specific vertex results that don't correspond - * exactly to any element of gl_vert_result. The values of this enum are - * assigned such that they don't conflict with gl_vert_result. + * exactly to any element of gl_varying_slot. The values of this enum are + * assigned such that they don't conflict with gl_varying_slot. */ typedef enum { - BRW_VERT_RESULT_NDC = VERT_RESULT_MAX, - BRW_VERT_RESULT_HPOS_DUPLICATE, - BRW_VERT_RESULT_PAD, + BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX, + BRW_VARYING_SLOT_POS_DUPLICATE, + BRW_VARYING_SLOT_PAD, /* * It's actually not a vert_result but just a _mark_ to let sf aware that * he need do something special to handle gl_PointCoord builtin variable * correctly. see compile_sf_prog() for more info. */ - BRW_VERT_RESULT_PNTC, - BRW_VERT_RESULT_MAX -} brw_vert_result; + BRW_VARYING_SLOT_PNTC, + BRW_VARYING_SLOT_MAX +} brw_varying_slot; /** - * Data structure recording the relationship between the gl_vert_result enum + * Data structure recording the relationship between the gl_varying_slot enum * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a * single octaword within the VUE (128 bits). * @@ -354,23 +354,23 @@ typedef enum */ struct brw_vue_map { /** - * Map from gl_vert_result value to VUE slot. For gl_vert_results that are + * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are * not stored in a slot (because they are not written, or because * additional processing is applied before storing them in the VUE), the * value is -1. */ - int vert_result_to_slot[BRW_VERT_RESULT_MAX]; + int vert_result_to_slot[BRW_VARYING_SLOT_MAX]; /** - * Map from VUE slot to gl_vert_result value. For slots that do not - * directly correspond to a gl_vert_result, the value comes from - * brw_vert_result. + * Map from VUE slot to gl_varying_slot value. For slots that do not + * directly correspond to a gl_varying_slot, the value comes from + * brw_varying_slot. * - * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this + * For slots that are not in use, the value is BRW_VARYING_SLOT_MAX (this * simplifies code that uses the value stored in slot_to_vert_result to * create a bit mask). */ - int slot_to_vert_result[BRW_VERT_RESULT_MAX]; + int slot_to_vert_result[BRW_VARYING_SLOT_MAX]; /** * Total number of VUE slots in use @@ -387,7 +387,8 @@ static inline GLuint brw_vue_slot_to_offset(GLuint slot) } /** - * Convert a vert_result into a byte offset within the VUE. + * Convert a vertex output (brw_varying_slot) into a byte offset within the + * VUE. */ static inline GLuint brw_vert_result_to_offset(struct brw_vue_map *vue_map, GLuint vert_result) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index def246c78c8..e5c0536d478 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1259,13 +1259,13 @@ fs_visitor::calculate_urb_setup() } } else { /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */ - for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) { + for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) { /* Point size is packed into the header, not as a general attribute */ - if (i == VERT_RESULT_PSIZ) + if (i == VARYING_SLOT_PSIZ) continue; if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { - int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i); + int fp_index = _mesa_vert_result_to_frag_attrib((gl_varying_slot) i); /* The back color slot is skipped when the front color is * also written to. In addition, some slots can be @@ -3001,7 +3001,7 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog) key.proj_attrib_mask |= BITFIELD64_BIT(i); if (intel->gen < 6) { - int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i); + int vp_index = _mesa_vert_result_to_frag_attrib((gl_varying_slot) i); if (vp_index >= 0) key.vp_outputs_written |= BITFIELD64_BIT(vp_index); diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index c6c6c140bdd..13289844035 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -197,7 +197,7 @@ static void populate_key( struct brw_context *brw, /* Make sure that the VUE slots won't overflow the unsigned chars in * key->transform_feedback_bindings[]. */ - STATIC_ASSERT(BRW_VERT_RESULT_MAX <= 256); + STATIC_ASSERT(BRW_VARYING_SLOT_MAX <= 256); /* Make sure that we don't need more binding table entries than we've * set aside for use in transform feedback. (We shouldn't, since we diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index 6e014fa65d7..f10d8e589ad 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -58,7 +58,7 @@ struct brw_gs_prog_key { /** * Map from the index of a transform feedback binding table entry to the - * gl_vert_result that should be streamed out through that binding table + * gl_varying_slot that should be streamed out through that binding table * entry. */ unsigned char transform_feedback_bindings[BRW_MAX_SOL_BINDINGS]; diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index 501cee42ea4..1e596d21fd8 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -446,8 +446,8 @@ gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, struct brw_reg vertex_slot = c->reg.vertex[vertex]; vertex_slot.nr += slot / 2; vertex_slot.subnr = (slot % 2) * 16; - /* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */ - vertex_slot.dw1.bits.swizzle = vert_result == VERT_RESULT_PSIZ + /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */ + vertex_slot.dw1.bits.swizzle = vert_result == VARYING_SLOT_PSIZ ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding]; brw_set_access_mode(p, BRW_ALIGN_16); brw_MOV(p, stride(c->reg.header, 4, 4, 1), diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c index eb361a97092..1132c9a4c00 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.c +++ b/src/mesa/drivers/dri/i965/brw_sf.c @@ -73,8 +73,8 @@ static void compile_sf_prog( struct brw_context *brw, * it manually to let SF shader generate the needed interpolation * coefficient for FS shader. */ - c.vue_map.vert_result_to_slot[BRW_VERT_RESULT_PNTC] = c.vue_map.num_slots; - c.vue_map.slot_to_vert_result[c.vue_map.num_slots++] = BRW_VERT_RESULT_PNTC; + c.vue_map.vert_result_to_slot[BRW_VARYING_SLOT_PNTC] = c.vue_map.num_slots; + c.vue_map.slot_to_vert_result[c.vue_map.num_slots++] = BRW_VARYING_SLOT_PNTC; } c.urb_entry_read_offset = brw_sf_compute_urb_entry_read_offset(intel); c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset; @@ -155,7 +155,7 @@ brw_upload_sf_prog(struct brw_context *brw) * edgeflag testing here, it is already done in the clip * program. */ - if (key.attrs & BITFIELD64_BIT(VERT_RESULT_EDGE)) + if (key.attrs & BITFIELD64_BIT(VARYING_SLOT_EDGE)) key.primitive = SF_UNFILLED_TRIS; else key.primitive = SF_TRIANGLES; diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c index 5f3673bec08..7f254cfc878 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_emit.c +++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c @@ -86,11 +86,11 @@ static void copy_bfc( struct brw_sf_compile *c, GLuint i; for (i = 0; i < 2; i++) { - if (have_attr(c, VERT_RESULT_COL0+i) && - have_attr(c, VERT_RESULT_BFC0+i)) + if (have_attr(c, VARYING_SLOT_COL0+i) && + have_attr(c, VARYING_SLOT_BFC0+i)) brw_MOV(p, - get_vert_result(c, vert, VERT_RESULT_COL0+i), - get_vert_result(c, vert, VERT_RESULT_BFC0+i)); + get_vert_result(c, vert, VARYING_SLOT_COL0+i), + get_vert_result(c, vert, VARYING_SLOT_BFC0+i)); } } @@ -109,8 +109,8 @@ static void do_twoside_color( struct brw_sf_compile *c ) * for user-supplied vertex programs, as t_vp_build.c always does * the right thing. */ - if (!(have_attr(c, VERT_RESULT_COL0) && have_attr(c, VERT_RESULT_BFC0)) && - !(have_attr(c, VERT_RESULT_COL1) && have_attr(c, VERT_RESULT_BFC1))) + if (!(have_attr(c, VARYING_SLOT_COL0) && have_attr(c, VARYING_SLOT_BFC0)) && + !(have_attr(c, VARYING_SLOT_COL1) && have_attr(c, VARYING_SLOT_BFC1))) return; /* Need to use BRW_EXECUTE_4 and also do an 4-wide compare in order @@ -138,8 +138,8 @@ static void do_twoside_color( struct brw_sf_compile *c ) * Flat shading */ -#define VERT_RESULT_COLOR_BITS (BITFIELD64_BIT(VERT_RESULT_COL0) | \ - BITFIELD64_BIT(VERT_RESULT_COL1)) +#define VARYING_SLOT_COLOR_BITS (BITFIELD64_BIT(VARYING_SLOT_COL0) | \ + BITFIELD64_BIT(VARYING_SLOT_COL1)) static void copy_colors( struct brw_sf_compile *c, struct brw_reg dst, @@ -148,7 +148,7 @@ static void copy_colors( struct brw_sf_compile *c, struct brw_compile *p = &c->func; GLuint i; - for (i = VERT_RESULT_COL0; i <= VERT_RESULT_COL1; i++) { + for (i = VARYING_SLOT_COL0; i <= VARYING_SLOT_COL1; i++) { if (have_attr(c,i)) brw_MOV(p, get_vert_result(c, dst, i), @@ -167,7 +167,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c ) struct brw_compile *p = &c->func; struct intel_context *intel = &p->brw->intel; struct brw_reg ip = brw_ip_reg(); - GLuint nr = _mesa_bitcount_64(c->key.attrs & VERT_RESULT_COLOR_BITS); + GLuint nr = _mesa_bitcount_64(c->key.attrs & VARYING_SLOT_COLOR_BITS); GLuint jmpi = 1; if (!nr) @@ -206,7 +206,7 @@ static void do_flatshade_line( struct brw_sf_compile *c ) struct brw_compile *p = &c->func; struct intel_context *intel = &p->brw->intel; struct brw_reg ip = brw_ip_reg(); - GLuint nr = _mesa_bitcount_64(c->key.attrs & VERT_RESULT_COLOR_BITS); + GLuint nr = _mesa_bitcount_64(c->key.attrs & VARYING_SLOT_COLOR_BITS); GLuint jmpi = 1; if (!nr) @@ -334,15 +334,15 @@ calculate_masks(struct brw_sf_compile *c, GLbitfield64 linear_mask; if (c->key.do_flat_shading) - persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VERT_RESULT_HPOS) | - BITFIELD64_BIT(VERT_RESULT_COL0) | - BITFIELD64_BIT(VERT_RESULT_COL1)); + persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VARYING_SLOT_POS) | + BITFIELD64_BIT(VARYING_SLOT_COL0) | + BITFIELD64_BIT(VARYING_SLOT_COL1)); else - persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VERT_RESULT_HPOS)); + persp_mask = c->key.attrs & ~(BITFIELD64_BIT(VARYING_SLOT_POS)); if (c->key.do_flat_shading) - linear_mask = c->key.attrs & ~(BITFIELD64_BIT(VERT_RESULT_COL0) | - BITFIELD64_BIT(VERT_RESULT_COL1)); + linear_mask = c->key.attrs & ~(BITFIELD64_BIT(VARYING_SLOT_COL0) | + BITFIELD64_BIT(VARYING_SLOT_COL1)); else linear_mask = c->key.attrs; @@ -358,7 +358,7 @@ calculate_masks(struct brw_sf_compile *c, /* Maybe only processs one attribute on the final round: */ - if (vert_reg_to_vert_result(c, reg, 1) != BRW_VERT_RESULT_MAX) { + if (vert_reg_to_vert_result(c, reg, 1) != BRW_VARYING_SLOT_MAX) { *pc |= 0xf0; if (persp_mask & BITFIELD64_BIT(vert_reg_to_vert_result(c, reg, 1))) @@ -381,20 +381,20 @@ calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg) uint16_t pc = 0; vert_result1 = vert_reg_to_vert_result(c, reg, 0); - if (vert_result1 >= VERT_RESULT_TEX0 && vert_result1 <= VERT_RESULT_TEX7) { - if (c->key.point_sprite_coord_replace & (1 << (vert_result1 - VERT_RESULT_TEX0))) + if (vert_result1 >= VARYING_SLOT_TEX0 && vert_result1 <= VARYING_SLOT_TEX7) { + if (c->key.point_sprite_coord_replace & (1 << (vert_result1 - VARYING_SLOT_TEX0))) pc |= 0x0f; } - if (vert_result1 == BRW_VERT_RESULT_PNTC) + if (vert_result1 == BRW_VARYING_SLOT_PNTC) pc |= 0x0f; vert_result2 = vert_reg_to_vert_result(c, reg, 1); - if (vert_result2 >= VERT_RESULT_TEX0 && vert_result2 <= VERT_RESULT_TEX7) { + if (vert_result2 >= VARYING_SLOT_TEX0 && vert_result2 <= VARYING_SLOT_TEX7) { if (c->key.point_sprite_coord_replace & (1 << (vert_result2 - - VERT_RESULT_TEX0))) + VARYING_SLOT_TEX0))) pc |= 0xf0; } - if (vert_result2 == BRW_VERT_RESULT_PNTC) + if (vert_result2 == BRW_VARYING_SLOT_PNTC) pc |= 0xf0; return pc; diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 86921a033d1..88a3e3b025f 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -299,8 +299,8 @@ public: /* Regs for vertex results. Generated at ir_variable visiting time * for the ir->location's used. */ - dst_reg output_reg[BRW_VERT_RESULT_MAX]; - const char *output_reg_annotation[BRW_VERT_RESULT_MAX]; + dst_reg output_reg[BRW_VARYING_SLOT_MAX]; + const char *output_reg_annotation[BRW_VARYING_SLOT_MAX]; int uniform_size[MAX_UNIFORMS]; int uniform_vector_size[MAX_UNIFORMS]; int uniforms; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 32de82b11f3..60575d70871 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -2379,11 +2379,11 @@ void vec4_visitor::emit_ndc_computation() { /* Get the position */ - src_reg pos = src_reg(output_reg[VERT_RESULT_HPOS]); + src_reg pos = src_reg(output_reg[VARYING_SLOT_POS]); /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */ dst_reg ndc = dst_reg(this, glsl_type::vec4_type); - output_reg[BRW_VERT_RESULT_NDC] = ndc; + output_reg[BRW_VARYING_SLOT_NDC] = ndc; current_annotation = "NDC"; dst_reg ndc_w = ndc; @@ -2402,7 +2402,7 @@ void vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) { if (intel->gen < 6 && - ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || + ((c->prog_data.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) || c->key.userclip_active || brw->has_negative_rhw_bug)) { dst_reg header1 = dst_reg(this, glsl_type::uvec4_type); dst_reg header1_w = header1; @@ -2411,8 +2411,8 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) emit(MOV(header1, 0u)); - if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { - src_reg psiz = src_reg(output_reg[VERT_RESULT_PSIZ]); + if (c->prog_data.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { + src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ]); current_annotation = "Point size"; emit(MUL(header1_w, psiz, src_reg((float)(1 << 11)))); @@ -2423,7 +2423,7 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) for (i = 0; i < c->key.nr_userclip_plane_consts; i++) { vec4_instruction *inst; - inst = emit(DP4(dst_null_f(), src_reg(output_reg[VERT_RESULT_HPOS]), + inst = emit(DP4(dst_null_f(), src_reg(output_reg[VARYING_SLOT_POS]), src_reg(this->userplane[i]))); inst->conditional_mod = BRW_CONDITIONAL_L; @@ -2441,13 +2441,13 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) * clipped against all fixed planes. */ if (brw->has_negative_rhw_bug) { - src_reg ndc_w = src_reg(output_reg[BRW_VERT_RESULT_NDC]); + src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC]); ndc_w.swizzle = BRW_SWIZZLE_WWWW; emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L)); vec4_instruction *inst; inst = emit(OR(header1_w, src_reg(header1_w), src_reg(1u << 6))); inst->predicate = BRW_PREDICATE_NORMAL; - inst = emit(MOV(output_reg[BRW_VERT_RESULT_NDC], src_reg(0.0f))); + inst = emit(MOV(output_reg[BRW_VARYING_SLOT_NDC], src_reg(0.0f))); inst->predicate = BRW_PREDICATE_NORMAL; } @@ -2456,9 +2456,9 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u)); } else { emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0))); - if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { + if (c->prog_data.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { emit(MOV(brw_writemask(reg, WRITEMASK_W), - src_reg(output_reg[VERT_RESULT_PSIZ]))); + src_reg(output_reg[VARYING_SLOT_PSIZ]))); } } } @@ -2486,10 +2486,10 @@ vec4_visitor::emit_clip_distances(struct brw_reg reg, int offset) * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping * if the user wrote to it; otherwise we use gl_Position. */ - gl_vert_result clip_vertex = VERT_RESULT_CLIP_VERTEX; + gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX; if (!(c->prog_data.outputs_written - & BITFIELD64_BIT(VERT_RESULT_CLIP_VERTEX))) { - clip_vertex = VERT_RESULT_HPOS; + & BITFIELD64_BIT(VARYING_SLOT_CLIP_VERTEX))) { + clip_vertex = VARYING_SLOT_POS; } for (int i = 0; i + offset < c->key.nr_userclip_plane_consts && i < 4; @@ -2503,16 +2503,16 @@ vec4_visitor::emit_clip_distances(struct brw_reg reg, int offset) void vec4_visitor::emit_generic_urb_slot(dst_reg reg, int vert_result) { - assert (vert_result < VERT_RESULT_MAX); + assert (vert_result < VARYING_SLOT_MAX); reg.type = output_reg[vert_result].type; current_annotation = output_reg_annotation[vert_result]; /* Copy the register, saturating if necessary */ vec4_instruction *inst = emit(MOV(reg, src_reg(output_reg[vert_result]))); - if ((vert_result == VERT_RESULT_COL0 || - vert_result == VERT_RESULT_COL1 || - vert_result == VERT_RESULT_BFC0 || - vert_result == VERT_RESULT_BFC1) && + if ((vert_result == VARYING_SLOT_COL0 || + vert_result == VARYING_SLOT_COL1 || + vert_result == VARYING_SLOT_BFC0 || + vert_result == VARYING_SLOT_BFC1) && c->key.clamp_vertex_color) { inst->saturate = true; } @@ -2526,30 +2526,30 @@ vec4_visitor::emit_urb_slot(int mrf, int vert_result) reg.type = BRW_REGISTER_TYPE_F; switch (vert_result) { - case VERT_RESULT_PSIZ: + case VARYING_SLOT_PSIZ: /* PSIZ is always in slot 0, and is coupled with other flags. */ current_annotation = "indices, point width, clip flags"; emit_psiz_and_flags(hw_reg); break; - case BRW_VERT_RESULT_NDC: + case BRW_VARYING_SLOT_NDC: current_annotation = "NDC"; - emit(MOV(reg, src_reg(output_reg[BRW_VERT_RESULT_NDC]))); + emit(MOV(reg, src_reg(output_reg[BRW_VARYING_SLOT_NDC]))); break; - case BRW_VERT_RESULT_HPOS_DUPLICATE: - case VERT_RESULT_HPOS: + case BRW_VARYING_SLOT_POS_DUPLICATE: + case VARYING_SLOT_POS: current_annotation = "gl_Position"; - emit(MOV(reg, src_reg(output_reg[VERT_RESULT_HPOS]))); + emit(MOV(reg, src_reg(output_reg[VARYING_SLOT_POS]))); break; - case VERT_RESULT_CLIP_DIST0: - case VERT_RESULT_CLIP_DIST1: + case VARYING_SLOT_CLIP_DIST0: + case VARYING_SLOT_CLIP_DIST1: if (this->c->key.uses_clip_distance) { emit_generic_urb_slot(reg, vert_result); } else { current_annotation = "user clip distances"; - emit_clip_distances(hw_reg, (vert_result - VERT_RESULT_CLIP_DIST0) * 4); + emit_clip_distances(hw_reg, (vert_result - VARYING_SLOT_CLIP_DIST0) * 4); } break; - case VERT_RESULT_EDGE: + case VARYING_SLOT_EDGE: /* This is present when doing unfilled polygons. We're supposed to copy * the edge flag from the user-provided vertex array * (glEdgeFlagPointer), or otherwise we'll copy from the current value @@ -2560,7 +2560,7 @@ vec4_visitor::emit_urb_slot(int mrf, int vert_result) emit(MOV(reg, src_reg(dst_reg(ATTR, VERT_ATTRIB_EDGEFLAG, glsl_type::float_type, WRITEMASK_XYZW)))); break; - case BRW_VERT_RESULT_PAD: + case BRW_VARYING_SLOT_PAD: /* No need to write to this slot */ break; default: diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp index 75799af0bbe..c9dc797d5d6 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp @@ -451,7 +451,7 @@ vec4_visitor::setup_vp_regs() /* PROGRAM_OUTPUT */ for (int slot = 0; slot < c->prog_data.vue_map.num_slots; slot++) { int vert_result = c->prog_data.vue_map.slot_to_vert_result[slot]; - if (vert_result == VERT_RESULT_PSIZ) + if (vert_result == VARYING_SLOT_PSIZ) output_reg[vert_result] = dst_reg(this, glsl_type::float_type); else output_reg[vert_result] = dst_reg(this, glsl_type::vec4_type); diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index 3daed19546c..7f060cd0a05 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -66,9 +66,9 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c) int i; vue_map->num_slots = 0; - for (i = 0; i < BRW_VERT_RESULT_MAX; ++i) { + for (i = 0; i < BRW_VARYING_SLOT_MAX; ++i) { vue_map->vert_result_to_slot[i] = -1; - vue_map->slot_to_vert_result[i] = BRW_VERT_RESULT_MAX; + vue_map->slot_to_vert_result[i] = BRW_VARYING_SLOT_MAX; } /* VUE header: format depends on chip generation and whether clipping is @@ -81,9 +81,9 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c) * dword 4-7 is ndc position * dword 8-11 is the first vertex data. */ - assign_vue_slot(vue_map, VERT_RESULT_PSIZ); - assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC); - assign_vue_slot(vue_map, VERT_RESULT_HPOS); + assign_vue_slot(vue_map, VARYING_SLOT_PSIZ); + assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC); + assign_vue_slot(vue_map, VARYING_SLOT_POS); break; case 5: /* There are 20 DWs (D0-D19) in VUE header on Ironlake: @@ -98,13 +98,13 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c) * contiguous with the other vert_results, so we make dword 24-27 a * duplicate copy of the 4D space position. */ - assign_vue_slot(vue_map, VERT_RESULT_PSIZ); - assign_vue_slot(vue_map, BRW_VERT_RESULT_NDC); - assign_vue_slot(vue_map, BRW_VERT_RESULT_HPOS_DUPLICATE); - assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0); - assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1); - assign_vue_slot(vue_map, BRW_VERT_RESULT_PAD); - assign_vue_slot(vue_map, VERT_RESULT_HPOS); + assign_vue_slot(vue_map, VARYING_SLOT_PSIZ); + assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC); + assign_vue_slot(vue_map, BRW_VARYING_SLOT_POS_DUPLICATE); + assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0); + assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1); + assign_vue_slot(vue_map, BRW_VARYING_SLOT_PAD); + assign_vue_slot(vue_map, VARYING_SLOT_POS); break; case 6: case 7: @@ -115,24 +115,24 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c) * enabled. * dword 8-11 or 16-19 is the first vertex element data we fill. */ - assign_vue_slot(vue_map, VERT_RESULT_PSIZ); - assign_vue_slot(vue_map, VERT_RESULT_HPOS); + assign_vue_slot(vue_map, VARYING_SLOT_PSIZ); + assign_vue_slot(vue_map, VARYING_SLOT_POS); if (c->key.userclip_active) { - assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST0); - assign_vue_slot(vue_map, VERT_RESULT_CLIP_DIST1); + assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0); + assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1); } /* front and back colors need to be consecutive so that we can use * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing * two-sided color. */ - if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0)) - assign_vue_slot(vue_map, VERT_RESULT_COL0); - if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0)) - assign_vue_slot(vue_map, VERT_RESULT_BFC0); - if (outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1)) - assign_vue_slot(vue_map, VERT_RESULT_COL1); - if (outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1)) - assign_vue_slot(vue_map, VERT_RESULT_BFC1); + if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_COL0)) + assign_vue_slot(vue_map, VARYING_SLOT_COL0); + if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_BFC0)) + assign_vue_slot(vue_map, VARYING_SLOT_BFC0); + if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_COL1)) + assign_vue_slot(vue_map, VARYING_SLOT_COL1); + if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_BFC1)) + assign_vue_slot(vue_map, VARYING_SLOT_BFC1); break; default: assert (!"VUE map not known for this chip generation"); @@ -143,14 +143,14 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vs_compile *c) * assign them contiguously. Don't reassign outputs that already have a * slot. * - * Also, prior to Gen6, don't assign a slot for VERT_RESULT_CLIP_VERTEX, - * since it is unsupported. In Gen6 and above, VERT_RESULT_CLIP_VERTEX may + * Also, prior to Gen6, don't assign a slot for VARYING_SLOT_CLIP_VERTEX, + * since it is unsupported. In Gen6 and above, VARYING_SLOT_CLIP_VERTEX may * be needed for transform feedback; since we don't want to have to * recompute the VUE map (and everything that depends on it) when transform * feedback is enabled or disabled, just go ahead and assign a slot for it. */ - for (int i = 0; i < VERT_RESULT_MAX; ++i) { - if (intel->gen < 6 && i == VERT_RESULT_CLIP_VERTEX) + for (int i = 0; i < VARYING_SLOT_MAX; ++i) { + if (intel->gen < 6 && i == VARYING_SLOT_CLIP_VERTEX) continue; if ((outputs_written & BITFIELD64_BIT(i)) && vue_map->vert_result_to_slot[i] == -1) { @@ -254,7 +254,7 @@ do_vs_prog(struct brw_context *brw, c.prog_data.inputs_read = vp->program.Base.InputsRead; if (c.key.copy_edgeflag) { - c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_EDGE); + c.prog_data.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE); c.prog_data.inputs_read |= VERT_BIT_EDGEFLAG; } @@ -267,7 +267,7 @@ do_vs_prog(struct brw_context *brw, */ for (i = 0; i < 8; i++) { if (c.key.point_coord_replace & (1 << i)) - c.prog_data.outputs_written |= BITFIELD64_BIT(VERT_RESULT_TEX0 + i); + c.prog_data.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_TEX0 + i); } } diff --git a/src/mesa/drivers/dri/i965/brw_vs_constval.c b/src/mesa/drivers/dri/i965/brw_vs_constval.c index f6ac256360e..e623b4c5e9f 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_constval.c +++ b/src/mesa/drivers/dri/i965/brw_vs_constval.c @@ -111,13 +111,13 @@ static GLubyte get_active( struct tracker *t, } /** - * Return the size (1,2,3 or 4) of the output/result for VERT_RESULT_idx. + * Return the size (1,2,3 or 4) of the output/result for VARYING_SLOT_idx. */ static GLubyte get_output_size( struct tracker *t, GLuint idx ) { GLubyte active; - assert(idx < VERT_RESULT_MAX); + assert(idx < VARYING_SLOT_MAX); active = t->active[PROGRAM_OUTPUT][idx]; if (active & (1<<3)) return 4; if (active & (1<<2)) return 3; @@ -133,17 +133,17 @@ static void calc_sizes( struct tracker *t ) GLint vertRes; if (t->twoside) { - t->active[PROGRAM_OUTPUT][VERT_RESULT_COL0] |= - t->active[PROGRAM_OUTPUT][VERT_RESULT_BFC0]; + t->active[PROGRAM_OUTPUT][VARYING_SLOT_COL0] |= + t->active[PROGRAM_OUTPUT][VARYING_SLOT_BFC0]; - t->active[PROGRAM_OUTPUT][VERT_RESULT_COL1] |= - t->active[PROGRAM_OUTPUT][VERT_RESULT_BFC1]; + t->active[PROGRAM_OUTPUT][VARYING_SLOT_COL1] |= + t->active[PROGRAM_OUTPUT][VARYING_SLOT_BFC1]; } /* Examine vertex program output sizes to set the size_masks[] info * which describes the fragment program input sizes. */ - for (vertRes = 0; vertRes < VERT_RESULT_MAX; vertRes++) { + for (vertRes = 0; vertRes < VARYING_SLOT_MAX; vertRes++) { /* map vertex program output index to fragment program input index */ GLint fragAttrib = _mesa_vert_result_to_frag_attrib(vertRes); diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c index 87f5bb10ebd..3da220ddb73 100644 --- a/src/mesa/drivers/dri/i965/gen6_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c @@ -57,7 +57,7 @@ get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset, int fs_attr, bool two_side_color, uint32_t *max_source_attr) { int vs_attr = _mesa_frag_attrib_to_vert_result(fs_attr); - if (vs_attr < 0 || vs_attr == VERT_RESULT_HPOS) { + if (vs_attr < 0 || vs_attr == VARYING_SLOT_POS) { /* These attributes will be overwritten by the fragment shader's * interpolation code (see emit_interp() in brw_wm_fp.c), so just let * them reference the first available attribute. @@ -71,10 +71,10 @@ get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset, /* If there was only a back color written but not front, use back * as the color instead of undefined */ - if (slot == -1 && vs_attr == VERT_RESULT_COL0) - slot = vue_map->vert_result_to_slot[VERT_RESULT_BFC0]; - if (slot == -1 && vs_attr == VERT_RESULT_COL1) - slot = vue_map->vert_result_to_slot[VERT_RESULT_BFC1]; + if (slot == -1 && vs_attr == VARYING_SLOT_COL0) + slot = vue_map->vert_result_to_slot[VARYING_SLOT_BFC0]; + if (slot == -1 && vs_attr == VARYING_SLOT_COL1) + slot = vue_map->vert_result_to_slot[VARYING_SLOT_BFC1]; if (slot == -1) { /* This attribute does not exist in the VUE--that means that the vertex @@ -107,10 +107,10 @@ get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset, * do back-facing swizzling. */ bool swizzling = two_side_color && - ((vue_map->slot_to_vert_result[slot] == VERT_RESULT_COL0 && - vue_map->slot_to_vert_result[slot+1] == VERT_RESULT_BFC0) || - (vue_map->slot_to_vert_result[slot] == VERT_RESULT_COL1 && - vue_map->slot_to_vert_result[slot+1] == VERT_RESULT_BFC1)); + ((vue_map->slot_to_vert_result[slot] == VARYING_SLOT_COL0 && + vue_map->slot_to_vert_result[slot+1] == VARYING_SLOT_BFC0) || + (vue_map->slot_to_vert_result[slot] == VARYING_SLOT_COL1 && + vue_map->slot_to_vert_result[slot+1] == VARYING_SLOT_BFC1)); /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */ if (*max_source_attr < source_attr + swizzling) diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c index 28cecf2d5cd..b55fccc0e0b 100644 --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c @@ -134,8 +134,8 @@ upload_3dstate_so_decl_list(struct brw_context *brw, unsigned component_mask = (1 << linked_xfb_info->Outputs[i].NumComponents) - 1; - /* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */ - if (vert_result == VERT_RESULT_PSIZ) { + /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */ + if (vert_result == VARYING_SLOT_PSIZ) { assert(linked_xfb_info->Outputs[i].NumComponents == 1); component_mask <<= 3; } else { diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 80963274526..f3cf34d275f 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -431,23 +431,23 @@ static GLboolean r200_run_tcl_render( struct gl_context *ctx, rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten; vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0]; - assert(vp_out & BITFIELD64_BIT(VERT_RESULT_HPOS)); + assert(vp_out & BITFIELD64_BIT(VARYING_SLOT_POS)); out_compsel = R200_OUTPUT_XYZW; - if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL0)) { + if (vp_out & BITFIELD64_BIT(VARYING_SLOT_COL0)) { out_compsel |= R200_OUTPUT_COLOR_0; } - if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL1)) { + if (vp_out & BITFIELD64_BIT(VARYING_SLOT_COL1)) { out_compsel |= R200_OUTPUT_COLOR_1; } - if (vp_out & BITFIELD64_BIT(VERT_RESULT_FOGC)) { + if (vp_out & BITFIELD64_BIT(VARYING_SLOT_FOGC)) { out_compsel |= R200_OUTPUT_DISCRETE_FOG; } - if (vp_out & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { + if (vp_out & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { out_compsel |= R200_OUTPUT_PT_SIZE; } - for (i = VERT_RESULT_TEX0; i < VERT_RESULT_TEX6; i++) { + for (i = VARYING_SLOT_TEX0; i < VARYING_SLOT_TEX6; i++) { if (vp_out & BITFIELD64_BIT(i)) { - out_compsel |= R200_OUTPUT_TEX_0 << (i - VERT_RESULT_TEX0); + out_compsel |= R200_OUTPUT_TEX_0 << (i - VARYING_SLOT_TEX0); } } if (rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] != out_compsel) { diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c index b371e80a4c7..ee867c29a7f 100644 --- a/src/mesa/drivers/dri/r200/r200_vertprog.c +++ b/src/mesa/drivers/dri/r200/r200_vertprog.c @@ -167,24 +167,24 @@ static unsigned long t_dst(struct prog_dst_register *dst) | R200_VSF_OUT_CLASS_TMP); case PROGRAM_OUTPUT: switch (dst->Index) { - case VERT_RESULT_HPOS: + case VARYING_SLOT_POS: return R200_VSF_OUT_CLASS_RESULT_POS; - case VERT_RESULT_COL0: + case VARYING_SLOT_COL0: return R200_VSF_OUT_CLASS_RESULT_COLOR; - case VERT_RESULT_COL1: + case VARYING_SLOT_COL1: return ((1 << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_RESULT_COLOR); - case VERT_RESULT_FOGC: + case VARYING_SLOT_FOGC: return R200_VSF_OUT_CLASS_RESULT_FOGC; - case VERT_RESULT_TEX0: - case VERT_RESULT_TEX1: - case VERT_RESULT_TEX2: - case VERT_RESULT_TEX3: - case VERT_RESULT_TEX4: - case VERT_RESULT_TEX5: - return (((dst->Index - VERT_RESULT_TEX0) << R200_VPI_OUT_REG_INDEX_SHIFT) + case VARYING_SLOT_TEX0: + case VARYING_SLOT_TEX1: + case VARYING_SLOT_TEX2: + case VARYING_SLOT_TEX3: + case VARYING_SLOT_TEX4: + case VARYING_SLOT_TEX5: + return (((dst->Index - VARYING_SLOT_TEX0) << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_RESULT_TEXC); - case VERT_RESULT_PSIZ: + case VARYING_SLOT_PSIZ: return R200_VSF_OUT_CLASS_RESULT_POINTSIZE; default: fprintf(stderr, "problem in %s, unknown dst output reg %d\n", __FUNCTION__, dst->Index); @@ -429,10 +429,10 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2 #endif if ((mesa_vp->Base.OutputsWritten & - ~((1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_COL0) | (1 << VERT_RESULT_COL1) | - (1 << VERT_RESULT_FOGC) | (1 << VERT_RESULT_TEX0) | (1 << VERT_RESULT_TEX1) | - (1 << VERT_RESULT_TEX2) | (1 << VERT_RESULT_TEX3) | (1 << VERT_RESULT_TEX4) | - (1 << VERT_RESULT_TEX5) | (1 << VERT_RESULT_PSIZ))) != 0) { + ~((1 << VARYING_SLOT_POS) | (1 << VARYING_SLOT_COL0) | (1 << VARYING_SLOT_COL1) | + (1 << VARYING_SLOT_FOGC) | (1 << VARYING_SLOT_TEX0) | (1 << VARYING_SLOT_TEX1) | + (1 << VARYING_SLOT_TEX2) | (1 << VARYING_SLOT_TEX3) | (1 << VARYING_SLOT_TEX4) | + (1 << VARYING_SLOT_TEX5) | (1 << VARYING_SLOT_PSIZ))) != 0) { if (R200_DEBUG & RADEON_FALLBACKS) { fprintf(stderr, "can't handle vert prog outputs 0x%llx\n", (unsigned long long) mesa_vp->Base.OutputsWritten); @@ -450,13 +450,13 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2 /* FIXME: is changing the prog safe to do here? */ if (mesa_vp->IsPositionInvariant && /* make sure we only do this once */ - !(mesa_vp->Base.OutputsWritten & (1 << VERT_RESULT_HPOS))) { + !(mesa_vp->Base.OutputsWritten & (1 << VARYING_SLOT_POS))) { _mesa_insert_mvp_code(ctx, mesa_vp); } /* for fogc, can't change mesa_vp, as it would hose swtnl, and exp with base e isn't directly available neither. */ - if ((mesa_vp->Base.OutputsWritten & (1 << VERT_RESULT_FOGC)) && !vp->fogpidx) { + if ((mesa_vp->Base.OutputsWritten & (1 << VARYING_SLOT_FOGC)) && !vp->fogpidx) { struct gl_program_parameter_list *paramList; gl_state_index tokens[STATE_LENGTH] = { STATE_FOG_PARAMS, 0, 0, 0, 0 }; paramList = mesa_vp->Base.Parameters; @@ -578,7 +578,7 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2 } } - if (!(mesa_vp->Base.OutputsWritten & (1 << VERT_RESULT_HPOS))) { + if (!(mesa_vp->Base.OutputsWritten & (1 << VARYING_SLOT_POS))) { if (R200_DEBUG & RADEON_FALLBACKS) { fprintf(stderr, "can't handle vert prog without position output\n"); } @@ -684,7 +684,7 @@ static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r2 dst = vpi->DstReg; if (dst.File == PROGRAM_OUTPUT && - dst.Index == VERT_RESULT_FOGC && + dst.Index == VARYING_SLOT_FOGC && dst.WriteMask & WRITEMASK_X) { fog_temp_i = u_temp_i; dst.File = PROGRAM_TEMPORARY; diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index b428d40fc1c..aa4bfa47963 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -348,7 +348,7 @@ dummy_enum_func(void) gl_frag_result fr = FRAG_RESULT_DEPTH; gl_texture_index ti = TEXTURE_2D_ARRAY_INDEX; gl_vert_attrib va = VERT_ATTRIB_POS; - gl_vert_result vr = VERT_RESULT_HPOS; + gl_varying_slot vs = VARYING_SLOT_POS; gl_geom_attrib ga = GEOM_ATTRIB_POSITION; gl_geom_result gr = GEOM_RESULT_POS; @@ -358,7 +358,7 @@ dummy_enum_func(void) (void) fr; (void) ti; (void) va; - (void) vr; + (void) vs; (void) ga; (void) gr; } @@ -677,7 +677,7 @@ static void check_context_limits(struct gl_context *ctx) { /* check that we don't exceed the size of various bitfields */ - assert(VERT_RESULT_MAX <= + assert(VARYING_SLOT_MAX <= (8 * sizeof(ctx->VertexProgram._Current->Base.OutputsWritten))); assert(FRAG_ATTRIB_MAX <= (8 * sizeof(ctx->FragmentProgram._Current->Base.InputsRead))); diff --git a/src/mesa/main/ff_fragment_shader.cpp b/src/mesa/main/ff_fragment_shader.cpp index 02b4707f078..1aea6e36d60 100644 --- a/src/mesa/main/ff_fragment_shader.cpp +++ b/src/mesa/main/ff_fragment_shader.cpp @@ -304,7 +304,6 @@ static GLuint translate_tex_src_bit( GLbitfield bit ) #define VERT_BIT_TEX_ANY (0xff << VERT_ATTRIB_TEX0) -#define VERT_RESULT_TEX_ANY (0xff << VERT_RESULT_TEX0) /** * Identify all possible varying inputs. The fragment program will @@ -398,12 +397,12 @@ static GLbitfield get_fp_input_mask( struct gl_context *ctx ) if (ctx->Point.PointSprite) vp_outputs |= FRAG_BITS_TEX_ANY; - if (vp_outputs & (1 << VERT_RESULT_COL0)) + if (vp_outputs & (1 << VARYING_SLOT_COL0)) fp_inputs |= FRAG_BIT_COL0; - if (vp_outputs & (1 << VERT_RESULT_COL1)) + if (vp_outputs & (1 << VARYING_SLOT_COL1)) fp_inputs |= FRAG_BIT_COL1; - fp_inputs |= (((vp_outputs & VERT_RESULT_TEX_ANY) >> VERT_RESULT_TEX0) + fp_inputs |= (((vp_outputs & VARYING_BITS_TEX_ANY) >> VARYING_SLOT_TEX0) << FRAG_ATTRIB_TEX0); } diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c index efdca015e99..3f08b098469 100644 --- a/src/mesa/main/ffvertex_prog.c +++ b/src/mesa/main/ffvertex_prog.c @@ -456,7 +456,7 @@ static struct ureg register_input( struct tnl_program *p, GLuint input ) /** - * \param input one of VERT_RESULT_x tokens. + * \param input one of VARYING_SLOT_x tokens. */ static struct ureg register_output( struct tnl_program *p, GLuint output ) { @@ -833,7 +833,7 @@ static struct ureg get_transformed_normal( struct tnl_program *p ) static void build_hpos( struct tnl_program *p ) { struct ureg pos = register_input( p, VERT_ATTRIB_POS ); - struct ureg hpos = register_output( p, VERT_RESULT_HPOS ); + struct ureg hpos = register_output( p, VARYING_SLOT_POS ); struct ureg mvp[4]; if (p->mvp_with_dp4) { @@ -1088,22 +1088,22 @@ static void build_lighting( struct tnl_program *p ) /* If no lights, still need to emit the scenecolor. */ { - struct ureg res0 = register_output( p, VERT_RESULT_COL0 ); + struct ureg res0 = register_output( p, VARYING_SLOT_COL0 ); emit_op1(p, OPCODE_MOV, res0, 0, _col0); } if (separate) { - struct ureg res1 = register_output( p, VERT_RESULT_COL1 ); + struct ureg res1 = register_output( p, VARYING_SLOT_COL1 ); emit_op1(p, OPCODE_MOV, res1, 0, _col1); } if (twoside) { - struct ureg res0 = register_output( p, VERT_RESULT_BFC0 ); + struct ureg res0 = register_output( p, VARYING_SLOT_BFC0 ); emit_op1(p, OPCODE_MOV, res0, 0, _bfc0); } if (twoside && separate) { - struct ureg res1 = register_output( p, VERT_RESULT_BFC1 ); + struct ureg res1 = register_output( p, VARYING_SLOT_BFC1 ); emit_op1(p, OPCODE_MOV, res1, 0, _bfc1); } @@ -1189,14 +1189,14 @@ static void build_lighting( struct tnl_program *p ) if (separate) { mask0 = WRITEMASK_XYZ; mask1 = WRITEMASK_XYZ; - res0 = register_output( p, VERT_RESULT_COL0 ); - res1 = register_output( p, VERT_RESULT_COL1 ); + res0 = register_output( p, VARYING_SLOT_COL0 ); + res1 = register_output( p, VARYING_SLOT_COL1 ); } else { mask0 = 0; mask1 = WRITEMASK_XYZ; res0 = _col0; - res1 = register_output( p, VERT_RESULT_COL0 ); + res1 = register_output( p, VARYING_SLOT_COL0 ); } } else { @@ -1244,14 +1244,14 @@ static void build_lighting( struct tnl_program *p ) if (separate) { mask0 = WRITEMASK_XYZ; mask1 = WRITEMASK_XYZ; - res0 = register_output( p, VERT_RESULT_BFC0 ); - res1 = register_output( p, VERT_RESULT_BFC1 ); + res0 = register_output( p, VARYING_SLOT_BFC0 ); + res1 = register_output( p, VARYING_SLOT_BFC1 ); } else { mask0 = 0; mask1 = WRITEMASK_XYZ; res0 = _bfc0; - res1 = register_output( p, VERT_RESULT_BFC0 ); + res1 = register_output( p, VARYING_SLOT_BFC0 ); } } else { @@ -1306,7 +1306,7 @@ static void build_lighting( struct tnl_program *p ) static void build_fog( struct tnl_program *p ) { - struct ureg fog = register_output(p, VERT_RESULT_FOGC); + struct ureg fog = register_output(p, VARYING_SLOT_FOGC); struct ureg input; if (p->state->fog_source_is_depth) { @@ -1417,7 +1417,7 @@ static void build_texture_transform( struct tnl_program *p ) p->state->unit[i].texmat_enabled) { GLuint texmat_enabled = p->state->unit[i].texmat_enabled; - struct ureg out = register_output(p, VERT_RESULT_TEX0 + i); + struct ureg out = register_output(p, VARYING_SLOT_TEX0 + i); struct ureg out_texgen = undef; if (p->state->unit[i].texgen_enabled) { @@ -1512,7 +1512,7 @@ static void build_texture_transform( struct tnl_program *p ) release_temps(p); } else { - emit_passthrough(p, VERT_ATTRIB_TEX0+i, VERT_RESULT_TEX0+i); + emit_passthrough(p, VERT_ATTRIB_TEX0+i, VARYING_SLOT_TEX0+i); } } } @@ -1526,7 +1526,7 @@ static void build_atten_pointsize( struct tnl_program *p ) struct ureg eye = get_eye_position_z(p); struct ureg state_size = register_param2(p, STATE_INTERNAL, STATE_POINT_SIZE_CLAMPED); struct ureg state_attenuation = register_param1(p, STATE_POINT_ATTENUATION); - struct ureg out = register_output(p, VERT_RESULT_PSIZ); + struct ureg out = register_output(p, VARYING_SLOT_PSIZ); struct ureg ut = get_temp(p); /* dist = |eyez| */ @@ -1562,7 +1562,7 @@ static void build_atten_pointsize( struct tnl_program *p ) static void build_array_pointsize( struct tnl_program *p ) { struct ureg in = register_input(p, VERT_ATTRIB_POINT_SIZE); - struct ureg out = register_output(p, VERT_RESULT_PSIZ); + struct ureg out = register_output(p, VARYING_SLOT_PSIZ); emit_op1(p, OPCODE_MOV, out, WRITEMASK_X, in); } @@ -1580,10 +1580,10 @@ static void build_tnl_program( struct tnl_program *p ) build_lighting(p); else { if (p->state->fragprog_inputs_read & FRAG_BIT_COL0) - emit_passthrough(p, VERT_ATTRIB_COLOR0, VERT_RESULT_COL0); + emit_passthrough(p, VERT_ATTRIB_COLOR0, VARYING_SLOT_COL0); if (p->state->fragprog_inputs_read & FRAG_BIT_COL1) - emit_passthrough(p, VERT_ATTRIB_COLOR1, VERT_RESULT_COL1); + emit_passthrough(p, VERT_ATTRIB_COLOR1, VARYING_SLOT_COL1); } } diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 37cc2daa5ab..1e62e19d69d 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -283,37 +283,6 @@ typedef enum /*@}*/ -/** - * Indexes for vertex program result attributes. Note that - * _mesa_vert_result_to_frag_attrib() and _mesa_frag_attrib_to_vert_result() make - * assumptions about the layout of this enum. - */ -typedef enum -{ - VERT_RESULT_HPOS = VARYING_SLOT_POS, - VERT_RESULT_COL0 = VARYING_SLOT_COL0, - VERT_RESULT_COL1 = VARYING_SLOT_COL1, - VERT_RESULT_FOGC = VARYING_SLOT_FOGC, - VERT_RESULT_TEX0 = VARYING_SLOT_TEX0, - VERT_RESULT_TEX1 = VARYING_SLOT_TEX1, - VERT_RESULT_TEX2 = VARYING_SLOT_TEX2, - VERT_RESULT_TEX3 = VARYING_SLOT_TEX3, - VERT_RESULT_TEX4 = VARYING_SLOT_TEX4, - VERT_RESULT_TEX5 = VARYING_SLOT_TEX5, - VERT_RESULT_TEX6 = VARYING_SLOT_TEX6, - VERT_RESULT_TEX7 = VARYING_SLOT_TEX7, - VERT_RESULT_PSIZ = VARYING_SLOT_PSIZ, - VERT_RESULT_BFC0 = VARYING_SLOT_BFC0, - VERT_RESULT_BFC1 = VARYING_SLOT_BFC1, - VERT_RESULT_EDGE = VARYING_SLOT_EDGE, - VERT_RESULT_CLIP_VERTEX = VARYING_SLOT_CLIP_VERTEX, - VERT_RESULT_CLIP_DIST0 = VARYING_SLOT_CLIP_DIST0, - VERT_RESULT_CLIP_DIST1 = VARYING_SLOT_CLIP_DIST1, - VERT_RESULT_VAR0 = VARYING_SLOT_VAR0, /**< shader varying */ - VERT_RESULT_MAX = VARYING_SLOT_MAX -} gl_vert_result; - - /*********************************************/ /** @@ -415,36 +384,34 @@ typedef enum /** - * Convert from a gl_vert_result value to the corresponding gl_frag_attrib. + * Convert from a gl_varying_slot value for a vertex output to the + * corresponding gl_frag_attrib. * - * VERT_RESULT_HPOS is converted to FRAG_ATTRIB_WPOS. - * - * gl_vert_result values which have no corresponding gl_frag_attrib - * (VERT_RESULT_PSIZ, VERT_RESULT_BFC0, VERT_RESULT_BFC1, and - * VERT_RESULT_EDGE) are converted to a value of -1. + * Varying output values which have no corresponding gl_frag_attrib + * (VARYING_SLOT_PSIZ, VARYING_SLOT_BFC0, VARYING_SLOT_BFC1, and + * VARYING_SLOT_EDGE) are converted to a value of -1. */ static inline int -_mesa_vert_result_to_frag_attrib(gl_vert_result vert_result) +_mesa_vert_result_to_frag_attrib(gl_varying_slot vert_result) { - if (vert_result <= VERT_RESULT_TEX7) + if (vert_result <= VARYING_SLOT_TEX7) return vert_result; - else if (vert_result < VERT_RESULT_CLIP_DIST0) + else if (vert_result < VARYING_SLOT_CLIP_DIST0) return -1; - else if (vert_result <= VERT_RESULT_CLIP_DIST1) - return vert_result - VERT_RESULT_CLIP_DIST0 + FRAG_ATTRIB_CLIP_DIST0; - else if (vert_result < VERT_RESULT_VAR0) + else if (vert_result <= VARYING_SLOT_CLIP_DIST1) + return vert_result - VARYING_SLOT_CLIP_DIST0 + FRAG_ATTRIB_CLIP_DIST0; + else if (vert_result < VARYING_SLOT_VAR0) return -1; else - return vert_result - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0; + return vert_result - VARYING_SLOT_VAR0 + FRAG_ATTRIB_VAR0; } /** - * Convert from a gl_frag_attrib value to the corresponding gl_vert_result. - * - * FRAG_ATTRIB_WPOS is converted to VERT_RESULT_HPOS. + * Convert from a gl_frag_attrib value to the corresponding gl_varying_slot + * for a vertex output. * - * gl_frag_attrib values which have no corresponding gl_vert_result + * gl_frag_attrib values which have no corresponding vertex output * (FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC) are converted to a value of -1. */ static inline int @@ -455,9 +422,9 @@ _mesa_frag_attrib_to_vert_result(gl_frag_attrib frag_attrib) else if (frag_attrib < FRAG_ATTRIB_CLIP_DIST0) return -1; else if (frag_attrib <= FRAG_ATTRIB_CLIP_DIST1) - return frag_attrib - FRAG_ATTRIB_CLIP_DIST0 + VERT_RESULT_CLIP_DIST0; + return frag_attrib - FRAG_ATTRIB_CLIP_DIST0 + VARYING_SLOT_CLIP_DIST0; else /* frag_attrib >= FRAG_ATTRIB_VAR0 */ - return frag_attrib - FRAG_ATTRIB_VAR0 + VERT_RESULT_VAR0; + return frag_attrib - FRAG_ATTRIB_VAR0 + VARYING_SLOT_VAR0; } diff --git a/src/mesa/program/prog_print.c b/src/mesa/program/prog_print.c index e5592cf3668..8617cfb5772 100644 --- a/src/mesa/program/prog_print.c +++ b/src/mesa/program/prog_print.c @@ -241,7 +241,7 @@ static const char * arb_output_attrib_string(GLint index, GLenum progType) { /* - * These strings should match the VERT_RESULT_x and FRAG_RESULT_x tokens. + * These strings should match the VARYING_SLOT_x and FRAG_RESULT_x tokens. */ static const char *const vertResults[] = { "result.position", @@ -256,13 +256,13 @@ arb_output_attrib_string(GLint index, GLenum progType) "result.texcoord[5]", "result.texcoord[6]", "result.texcoord[7]", - "result.pointsize", /* VERT_RESULT_PSIZ */ - "result.(thirteen)", /* VERT_RESULT_BFC0 */ - "result.(fourteen)", /* VERT_RESULT_BFC1 */ - "result.(fifteen)", /* VERT_RESULT_EDGE */ - "result.(sixteen)", /* VERT_RESULT_CLIP_VERTEX */ - "result.(seventeen)", /* VERT_RESULT_CLIP_DIST0 */ - "result.(eighteen)", /* VERT_RESULT_CLIP_DIST1 */ + "result.pointsize", /* VARYING_SLOT_PSIZ */ + "result.(thirteen)", /* VARYING_SLOT_BFC0 */ + "result.(fourteen)", /* VARYING_SLOT_BFC1 */ + "result.(fifteen)", /* VARYING_SLOT_EDGE */ + "result.(sixteen)", /* VARYING_SLOT_CLIP_VERTEX */ + "result.(seventeen)", /* VARYING_SLOT_CLIP_DIST0 */ + "result.(eighteen)", /* VARYING_SLOT_CLIP_DIST1 */ "result.(nineteen)", /* VARYING_SLOT_PRIMITIVE_ID */ "result.(twenty)", /* VARYING_SLOT_LAYER */ "result.(twenty-one)", /* VARYING_SLOT_FACE */ @@ -315,10 +315,10 @@ arb_output_attrib_string(GLint index, GLenum progType) }; /* sanity checks */ - STATIC_ASSERT(Elements(vertResults) == VERT_RESULT_MAX); + STATIC_ASSERT(Elements(vertResults) == VARYING_SLOT_MAX); STATIC_ASSERT(Elements(fragResults) == FRAG_RESULT_MAX); - assert(strcmp(vertResults[VERT_RESULT_HPOS], "result.position") == 0); - assert(strcmp(vertResults[VERT_RESULT_VAR0], "result.varying[0]") == 0); + assert(strcmp(vertResults[VARYING_SLOT_POS], "result.position") == 0); + assert(strcmp(vertResults[VARYING_SLOT_VAR0], "result.varying[0]") == 0); assert(strcmp(fragResults[FRAG_RESULT_DATA0], "result.color[0]") == 0); if (progType == GL_VERTEX_PROGRAM_ARB) { diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c index fb0aeb7edaa..e235d6ce68a 100644 --- a/src/mesa/program/program.c +++ b/src/mesa/program/program.c @@ -947,7 +947,7 @@ _mesa_valid_register_index(const struct gl_context *ctx, switch (shaderType) { case MESA_SHADER_VERTEX: - return index < VERT_RESULT_VAR0 + (GLint) ctx->Const.MaxVarying; + return index < VARYING_SLOT_VAR0 + (GLint) ctx->Const.MaxVarying; case MESA_SHADER_FRAGMENT: return index < FRAG_RESULT_DATA0 + (GLint) ctx->Const.MaxDrawBuffers; case MESA_SHADER_GEOMETRY: diff --git a/src/mesa/program/program_parse.y b/src/mesa/program/program_parse.y index 025b54706da..c9df3e64f90 100644 --- a/src/mesa/program/program_parse.y +++ b/src/mesa/program/program_parse.y @@ -643,7 +643,7 @@ maskedDstReg: dstReg optionalMask optionalCcMask * set in fragment program mode, so it is somewhat irrelevant. */ if (state->option.PositionInvariant - && ($$.Index == VERT_RESULT_HPOS)) { + && ($$.Index == VARYING_SLOT_POS)) { yyerror(& @1, state, "position-invariant programs cannot " "write position"); YYERROR; @@ -2005,7 +2005,7 @@ OUTPUT_statement: optVarSize OUTPUT IDENTIFIER '=' resultBinding resultBinding: RESULT POSITION { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_HPOS; + $$ = VARYING_SLOT_POS; } else { yyerror(& @2, state, "invalid program result name"); YYERROR; @@ -2014,7 +2014,7 @@ resultBinding: RESULT POSITION | RESULT FOGCOORD { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_FOGC; + $$ = VARYING_SLOT_FOGC; } else { yyerror(& @2, state, "invalid program result name"); YYERROR; @@ -2027,7 +2027,7 @@ resultBinding: RESULT POSITION | RESULT POINTSIZE { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_PSIZ; + $$ = VARYING_SLOT_PSIZ; } else { yyerror(& @2, state, "invalid program result name"); YYERROR; @@ -2036,7 +2036,7 @@ resultBinding: RESULT POSITION | RESULT TEXCOORD optTexCoordUnitNum { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_TEX0 + $3; + $$ = VARYING_SLOT_TEX0 + $3; } else { yyerror(& @2, state, "invalid program result name"); YYERROR; @@ -2062,7 +2062,7 @@ resultColBinding: COLOR optResultFaceType optResultColorType optResultFaceType: { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_COL0; + $$ = VARYING_SLOT_COL0; } else { if (state->option.DrawBuffers) $$ = FRAG_RESULT_DATA0; @@ -2101,7 +2101,7 @@ optResultFaceType: | FRONT { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_COL0; + $$ = VARYING_SLOT_COL0; } else { yyerror(& @1, state, "invalid program result name"); YYERROR; @@ -2110,7 +2110,7 @@ optResultFaceType: | BACK { if (state->mode == ARB_vertex) { - $$ = VERT_RESULT_BFC0; + $$ = VARYING_SLOT_BFC0; } else { yyerror(& @1, state, "invalid program result name"); YYERROR; diff --git a/src/mesa/program/programopt.c b/src/mesa/program/programopt.c index 2a37021988a..19890802b79 100644 --- a/src/mesa/program/programopt.c +++ b/src/mesa/program/programopt.c @@ -89,7 +89,7 @@ _mesa_insert_mvp_dp4_code(struct gl_context *ctx, struct gl_vertex_program *vpro for (i = 0; i < 4; i++) { newInst[i].Opcode = OPCODE_DP4; newInst[i].DstReg.File = PROGRAM_OUTPUT; - newInst[i].DstReg.Index = VERT_RESULT_HPOS; + newInst[i].DstReg.Index = VARYING_SLOT_POS; newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR; newInst[i].SrcReg[0].Index = mvpRef[i]; @@ -109,7 +109,7 @@ _mesa_insert_mvp_dp4_code(struct gl_context *ctx, struct gl_vertex_program *vpro vprog->Base.Instructions = newInst; vprog->Base.NumInstructions = newLen; vprog->Base.InputsRead |= VERT_BIT_POS; - vprog->Base.OutputsWritten |= BITFIELD64_BIT(VERT_RESULT_HPOS); + vprog->Base.OutputsWritten |= BITFIELD64_BIT(VARYING_SLOT_POS); } @@ -188,7 +188,7 @@ _mesa_insert_mvp_mad_code(struct gl_context *ctx, struct gl_vertex_program *vpro newInst[3].Opcode = OPCODE_MAD; newInst[3].DstReg.File = PROGRAM_OUTPUT; - newInst[3].DstReg.Index = VERT_RESULT_HPOS; + newInst[3].DstReg.Index = VARYING_SLOT_POS; newInst[3].DstReg.WriteMask = WRITEMASK_XYZW; newInst[3].SrcReg[0].File = PROGRAM_INPUT; newInst[3].SrcReg[0].Index = VERT_ATTRIB_POS; @@ -211,7 +211,7 @@ _mesa_insert_mvp_mad_code(struct gl_context *ctx, struct gl_vertex_program *vpro vprog->Base.Instructions = newInst; vprog->Base.NumInstructions = newLen; vprog->Base.InputsRead |= VERT_BIT_POS; - vprog->Base.OutputsWritten |= BITFIELD64_BIT(VERT_RESULT_HPOS); + vprog->Base.OutputsWritten |= BITFIELD64_BIT(VARYING_SLOT_POS); } @@ -507,7 +507,7 @@ void _mesa_remove_output_reads(struct gl_program *prog, gl_register_file type) { GLuint i; - GLint outputMap[VERT_RESULT_MAX]; + GLint outputMap[VARYING_SLOT_MAX]; GLuint numVaryingReads = 0; GLboolean usedTemps[MAX_PROGRAM_TEMPS]; GLuint firstTemp = 0; @@ -517,7 +517,7 @@ _mesa_remove_output_reads(struct gl_program *prog, gl_register_file type) assert(type == PROGRAM_OUTPUT); - for (i = 0; i < VERT_RESULT_MAX; i++) + for (i = 0; i < VARYING_SLOT_MAX; i++) outputMap[i] = -1; /* look for instructions which read from varying vars */ @@ -576,7 +576,7 @@ _mesa_remove_output_reads(struct gl_program *prog, gl_register_file type) /* insert new MOV instructions here */ inst = prog->Instructions + endPos; - for (var = 0; var < VERT_RESULT_MAX; var++) { + for (var = 0; var < VARYING_SLOT_MAX; var++) { if (outputMap[var] >= 0) { /* MOV VAR[var], TEMP[tmp]; */ inst->Opcode = OPCODE_MOV; @@ -657,7 +657,7 @@ _mesa_nop_vertex_program(struct gl_context *ctx, struct gl_vertex_program *prog) inst[0].Opcode = OPCODE_MOV; inst[0].DstReg.File = PROGRAM_OUTPUT; - inst[0].DstReg.Index = VERT_RESULT_COL0; + inst[0].DstReg.Index = VARYING_SLOT_COL0; inst[0].SrcReg[0].File = PROGRAM_INPUT; if (prog->Base.InputsRead & VERT_BIT_COLOR0) inputAttr = VERT_ATTRIB_COLOR0; @@ -673,7 +673,7 @@ _mesa_nop_vertex_program(struct gl_context *ctx, struct gl_vertex_program *prog) prog->Base.Instructions = inst; prog->Base.NumInstructions = 2; prog->Base.InputsRead = BITFIELD64_BIT(inputAttr); - prog->Base.OutputsWritten = BITFIELD64_BIT(VERT_RESULT_COL0); + prog->Base.OutputsWritten = BITFIELD64_BIT(VARYING_SLOT_COL0); /* * Now insert code to do standard modelview/projection transformation. diff --git a/src/mesa/state_tracker/st_atom_rasterizer.c b/src/mesa/state_tracker/st_atom_rasterizer.c index 0e2a152cd57..c4b95e83b47 100644 --- a/src/mesa/state_tracker/st_atom_rasterizer.c +++ b/src/mesa/state_tracker/st_atom_rasterizer.c @@ -183,7 +183,7 @@ static void update_raster_state( struct st_context *st ) */ if (vertProg) { if (vertProg->Base.Id == 0) { - if (vertProg->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { + if (vertProg->Base.OutputsWritten & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { /* generated program which emits point size */ raster->point_size_per_vertex = TRUE; } diff --git a/src/mesa/state_tracker/st_cb_feedback.c b/src/mesa/state_tracker/st_cb_feedback.c index 9092e3a7127..7a8fde46515 100644 --- a/src/mesa/state_tracker/st_cb_feedback.c +++ b/src/mesa/state_tracker/st_cb_feedback.c @@ -97,13 +97,13 @@ feedback_vertex(struct gl_context *ctx, const struct draw_context *draw, * color and texcoord attribs to use here. */ - slot = st->vertex_result_to_slot[VERT_RESULT_COL0]; + slot = st->vertex_result_to_slot[VARYING_SLOT_COL0]; if (slot != ~0U) color = v->data[slot]; else color = ctx->Current.Attrib[VERT_ATTRIB_COLOR0]; - slot = st->vertex_result_to_slot[VERT_RESULT_TEX0]; + slot = st->vertex_result_to_slot[VARYING_SLOT_TEX0]; if (slot != ~0U) texcoord = v->data[slot]; else diff --git a/src/mesa/state_tracker/st_cb_rasterpos.c b/src/mesa/state_tracker/st_cb_rasterpos.c index fb4a62ee33a..4731f26482b 100644 --- a/src/mesa/state_tracker/st_cb_rasterpos.c +++ b/src/mesa/state_tracker/st_cb_rasterpos.c @@ -154,16 +154,16 @@ rastpos_point(struct draw_stage *stage, struct prim_header *prim) /* update other raster attribs */ update_attrib(ctx, outputMapping, prim->v[0], ctx->Current.RasterColor, - VERT_RESULT_COL0, VERT_ATTRIB_COLOR0); + VARYING_SLOT_COL0, VERT_ATTRIB_COLOR0); update_attrib(ctx, outputMapping, prim->v[0], ctx->Current.RasterSecondaryColor, - VERT_RESULT_COL1, VERT_ATTRIB_COLOR1); + VARYING_SLOT_COL1, VERT_ATTRIB_COLOR1); for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) { update_attrib(ctx, outputMapping, prim->v[0], ctx->Current.RasterTexCoords[i], - VERT_RESULT_TEX0 + i, VERT_ATTRIB_TEX0 + i); + VARYING_SLOT_TEX0 + i, VERT_ATTRIB_TEX0 + i); } if (ctx->RenderMode == GL_SELECT) { diff --git a/src/mesa/state_tracker/st_context.h b/src/mesa/state_tracker/st_context.h index a7b6cb53502..b9a98cd051d 100644 --- a/src/mesa/state_tracker/st_context.h +++ b/src/mesa/state_tracker/st_context.h @@ -126,7 +126,7 @@ struct st_context GLboolean missing_textures; GLboolean vertdata_edgeflags; - /** Mapping from VERT_RESULT_x to post-transformed vertex slot */ + /** Mapping from VARYING_SLOT_x to post-transformed vertex slot */ const GLuint *vertex_result_to_slot; struct st_vertex_program *vp; /**< Currently bound vertex program */ diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 131ecb22a56..ebb806864dd 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -4144,7 +4144,7 @@ dst_register(struct st_translate *t, case PROGRAM_OUTPUT: if (t->procType == TGSI_PROCESSOR_VERTEX) - assert(index < VERT_RESULT_MAX); + assert(index < VARYING_SLOT_MAX); else if (t->procType == TGSI_PROCESSOR_FRAGMENT) assert(index < FRAG_RESULT_MAX); else @@ -4246,10 +4246,10 @@ translate_dst(struct st_translate *t, case TGSI_PROCESSOR_VERTEX: /* XXX if the geometry shader is present, this must be done there * instead of here. */ - if (dst_reg->index == VERT_RESULT_COL0 || - dst_reg->index == VERT_RESULT_COL1 || - dst_reg->index == VERT_RESULT_BFC0 || - dst_reg->index == VERT_RESULT_BFC1) { + if (dst_reg->index == VARYING_SLOT_COL0 || + dst_reg->index == VARYING_SLOT_COL1 || + dst_reg->index == VARYING_SLOT_BFC0 || + dst_reg->index == VARYING_SLOT_BFC1) { dst = ureg_saturate(dst); } break; @@ -4624,7 +4624,7 @@ static void emit_edgeflags(struct st_translate *t) { struct ureg_program *ureg = t->ureg; - struct ureg_dst edge_dst = t->outputs[t->outputMapping[VERT_RESULT_EDGE]]; + struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]]; struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]]; ureg_MOV(ureg, edge_dst, edge_src); diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c index e326bcc7031..e494f45e8f3 100644 --- a/src/mesa/state_tracker/st_mesa_to_tgsi.c +++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c @@ -175,7 +175,7 @@ dst_register( struct st_translate *t, case PROGRAM_OUTPUT: if (t->procType == TGSI_PROCESSOR_VERTEX) - assert(index < VERT_RESULT_MAX); + assert(index < VARYING_SLOT_MAX); else if (t->procType == TGSI_PROCESSOR_FRAGMENT) assert(index < FRAG_RESULT_MAX); else @@ -310,10 +310,10 @@ translate_dst( struct st_translate *t, case TGSI_PROCESSOR_VERTEX: /* XXX if the geometry shader is present, this must be done there * instead of here. */ - if (DstReg->Index == VERT_RESULT_COL0 || - DstReg->Index == VERT_RESULT_COL1 || - DstReg->Index == VERT_RESULT_BFC0 || - DstReg->Index == VERT_RESULT_BFC1) { + if (DstReg->Index == VARYING_SLOT_COL0 || + DstReg->Index == VARYING_SLOT_COL1 || + DstReg->Index == VARYING_SLOT_BFC0 || + DstReg->Index == VARYING_SLOT_BFC1) { dst = ureg_saturate(dst); } break; @@ -979,7 +979,7 @@ emit_edgeflags( struct st_translate *t, const struct gl_program *program ) { struct ureg_program *ureg = t->ureg; - struct ureg_dst edge_dst = t->outputs[t->outputMapping[VERT_RESULT_EDGE]]; + struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]]; struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]]; ureg_MOV( ureg, edge_dst, edge_src ); diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c index f56f7cb1c5d..109d4215001 100644 --- a/src/mesa/state_tracker/st_program.c +++ b/src/mesa/state_tracker/st_program.c @@ -168,7 +168,7 @@ st_release_gp_variants(struct st_context *st, struct st_geometry_program *stgp) /** * Translate a Mesa vertex shader into a TGSI shader. - * \param outputMapping to map vertex program output registers (VERT_RESULT_x) + * \param outputMapping to map vertex program output registers (VARYING_SLOT_x) * to TGSI output slots * \param tokensOut destination for TGSI tokens * \return pointer to cached pipe_shader object. @@ -205,7 +205,7 @@ st_prepare_vertex_program(struct gl_context *ctx, /* Compute mapping of vertex program outputs to slots. */ - for (attr = 0; attr < VERT_RESULT_MAX; attr++) { + for (attr = 0; attr < VARYING_SLOT_MAX; attr++) { if ((stvp->Base.Base.OutputsWritten & BITFIELD64_BIT(attr)) == 0) { stvp->result_to_output[attr] = ~0; } @@ -215,76 +215,76 @@ st_prepare_vertex_program(struct gl_context *ctx, stvp->result_to_output[attr] = slot; switch (attr) { - case VERT_RESULT_HPOS: + case VARYING_SLOT_POS: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_POSITION; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_COL0: + case VARYING_SLOT_COL0: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_COLOR; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_COL1: + case VARYING_SLOT_COL1: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_COLOR; stvp->output_semantic_index[slot] = 1; break; - case VERT_RESULT_BFC0: + case VARYING_SLOT_BFC0: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_BCOLOR; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_BFC1: + case VARYING_SLOT_BFC1: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_BCOLOR; stvp->output_semantic_index[slot] = 1; break; - case VERT_RESULT_FOGC: + case VARYING_SLOT_FOGC: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_FOG; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_PSIZ: + case VARYING_SLOT_PSIZ: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_PSIZE; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_CLIP_DIST0: + case VARYING_SLOT_CLIP_DIST0: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_CLIPDIST; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_CLIP_DIST1: + case VARYING_SLOT_CLIP_DIST1: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_CLIPDIST; stvp->output_semantic_index[slot] = 1; break; - case VERT_RESULT_EDGE: + case VARYING_SLOT_EDGE: assert(0); break; - case VERT_RESULT_CLIP_VERTEX: + case VARYING_SLOT_CLIP_VERTEX: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_CLIPVERTEX; stvp->output_semantic_index[slot] = 0; break; - case VERT_RESULT_TEX0: - case VERT_RESULT_TEX1: - case VERT_RESULT_TEX2: - case VERT_RESULT_TEX3: - case VERT_RESULT_TEX4: - case VERT_RESULT_TEX5: - case VERT_RESULT_TEX6: - case VERT_RESULT_TEX7: + case VARYING_SLOT_TEX0: + case VARYING_SLOT_TEX1: + case VARYING_SLOT_TEX2: + case VARYING_SLOT_TEX3: + case VARYING_SLOT_TEX4: + case VARYING_SLOT_TEX5: + case VARYING_SLOT_TEX6: + case VARYING_SLOT_TEX7: stvp->output_semantic_name[slot] = TGSI_SEMANTIC_GENERIC; - stvp->output_semantic_index[slot] = attr - VERT_RESULT_TEX0; + stvp->output_semantic_index[slot] = attr - VARYING_SLOT_TEX0; break; - case VERT_RESULT_VAR0: + case VARYING_SLOT_VAR0: default: - assert(attr < VERT_RESULT_MAX); + assert(attr < VARYING_SLOT_MAX); stvp->output_semantic_name[slot] = TGSI_SEMANTIC_GENERIC; stvp->output_semantic_index[slot] = (FRAG_ATTRIB_VAR0 - FRAG_ATTRIB_TEX0 + attr - - VERT_RESULT_VAR0); + VARYING_SLOT_VAR0); break; } } } /* similar hack to above, presetup potentially unused edgeflag output */ - stvp->result_to_output[VERT_RESULT_EDGE] = stvp->num_outputs; + stvp->result_to_output[VARYING_SLOT_EDGE] = stvp->num_outputs; stvp->output_semantic_name[stvp->num_outputs] = TGSI_SEMANTIC_EDGEFLAG; stvp->output_semantic_index[stvp->num_outputs] = 0; } diff --git a/src/mesa/state_tracker/st_program.h b/src/mesa/state_tracker/st_program.h index 23a262cccc0..3be73977fc2 100644 --- a/src/mesa/state_tracker/st_program.h +++ b/src/mesa/state_tracker/st_program.h @@ -152,10 +152,10 @@ struct st_vertex_program GLuint index_to_input[PIPE_MAX_SHADER_INPUTS]; GLuint num_inputs; - /** Maps VERT_RESULT_x to slot */ - GLuint result_to_output[VERT_RESULT_MAX]; - ubyte output_semantic_name[VERT_RESULT_MAX]; - ubyte output_semantic_index[VERT_RESULT_MAX]; + /** Maps VARYING_SLOT_x to slot */ + GLuint result_to_output[VARYING_SLOT_MAX]; + ubyte output_semantic_name[VARYING_SLOT_MAX]; + ubyte output_semantic_index[VARYING_SLOT_MAX]; GLuint num_outputs; /** List of translated variants of this vertex program. diff --git a/src/mesa/tnl/t_context.c b/src/mesa/tnl/t_context.c index df3a11666a8..d7b62fa415e 100644 --- a/src/mesa/tnl/t_context.c +++ b/src/mesa/tnl/t_context.c @@ -177,7 +177,7 @@ _tnl_InvalidateState( struct gl_context *ctx, GLuint new_state ) if (vp) { GLuint i; for (i = 0; i < MAX_VARYING; i++) { - if (vp->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_VAR0 + i)) { + if (vp->Base.OutputsWritten & BITFIELD64_BIT(VARYING_SLOT_VAR0 + i)) { tnl->render_inputs_bitset |= BITFIELD64_BIT(_TNL_ATTRIB_GENERIC(i)); } } diff --git a/src/mesa/tnl/t_context.h b/src/mesa/tnl/t_context.h index 62dde4f4e64..c9ff1246daa 100644 --- a/src/mesa/tnl/t_context.h +++ b/src/mesa/tnl/t_context.h @@ -133,7 +133,7 @@ enum { _TNL_ATTRIB_MAT_FRONT_INDEXES = 27, _TNL_ATTRIB_MAT_BACK_INDEXES = 28, - /* This is really a VERT_RESULT, not an attrib. Need to fix + /* This is really a VARYING_SLOT, not an attrib. Need to fix * tnl to understand the difference. */ _TNL_ATTRIB_POINTSIZE = 16, diff --git a/src/mesa/tnl/t_pipeline.c b/src/mesa/tnl/t_pipeline.c index 881d5d5f535..806d9ca6ec1 100644 --- a/src/mesa/tnl/t_pipeline.c +++ b/src/mesa/tnl/t_pipeline.c @@ -94,7 +94,7 @@ static GLuint check_output_changes( struct gl_context *ctx ) #if 0 TNLcontext *tnl = TNL_CONTEXT(ctx); - for (i = 0; i < VERT_RESULT_MAX; i++) { + for (i = 0; i < VARYING_SLOT_MAX; i++) { if (tnl->vb.ResultPtr[i]->size != tnl->last_result_size[i] || tnl->vb.ResultPtr[i]->stride != tnl->last_result_stride[i]) { tnl->last_result_size[i] = tnl->vb.ResultPtr[i]->size; diff --git a/src/mesa/tnl/t_vb_program.c b/src/mesa/tnl/t_vb_program.c index 8ff300cd7f5..452285f6b9e 100644 --- a/src/mesa/tnl/t_vb_program.c +++ b/src/mesa/tnl/t_vb_program.c @@ -63,7 +63,7 @@ check_float(float x) */ struct vp_stage_data { /** The results of running the vertex program go into these arrays. */ - GLvector4f results[VERT_RESULT_MAX]; + GLvector4f results[VARYING_SLOT_MAX]; GLvector4f ndcCoords; /**< normalized device coords */ GLubyte *clipmask; /**< clip flags */ @@ -300,7 +300,7 @@ run_vp( struct gl_context *ctx, struct tnl_pipeline_stage *stage ) struct vertex_buffer *VB = &tnl->vb; struct gl_vertex_program *program = ctx->VertexProgram._Current; struct gl_program_machine *machine = &store->machine; - GLuint outputs[VERT_RESULT_MAX], numOutputs; + GLuint outputs[VARYING_SLOT_MAX], numOutputs; GLuint i, j; if (!program) @@ -311,7 +311,7 @@ run_vp( struct gl_context *ctx, struct tnl_pipeline_stage *stage ) /* make list of outputs to save some time below */ numOutputs = 0; - for (i = 0; i < VERT_RESULT_MAX; i++) { + for (i = 0; i < VARYING_SLOT_MAX; i++) { if (program->Base.OutputsWritten & BITFIELD64_BIT(i)) { outputs[numOutputs++] = i; } @@ -321,7 +321,7 @@ run_vp( struct gl_context *ctx, struct tnl_pipeline_stage *stage ) * memory that would never be used if we don't run the software tnl pipeline. */ if (!store->results[0].storage) { - for (i = 0; i < VERT_RESULT_MAX; i++) { + for (i = 0; i < VARYING_SLOT_MAX; i++) { assert(!store->results[i].storage); _mesa_vector4f_alloc( &store->results[i], 0, VB->Size, 32 ); store->results[i].size = 4; @@ -386,10 +386,10 @@ run_vp( struct gl_context *ctx, struct tnl_pipeline_stage *stage ) } /* FOGC is a special case. Fragment shader expects (f,0,0,1) */ - if (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_FOGC)) { - store->results[VERT_RESULT_FOGC].data[i][1] = 0.0; - store->results[VERT_RESULT_FOGC].data[i][2] = 0.0; - store->results[VERT_RESULT_FOGC].data[i][3] = 1.0; + if (program->Base.OutputsWritten & BITFIELD64_BIT(VARYING_SLOT_FOGC)) { + store->results[VARYING_SLOT_FOGC].data[i][1] = 0.0; + store->results[VARYING_SLOT_FOGC].data[i][2] = 0.0; + store->results[VARYING_SLOT_FOGC].data[i][3] = 1.0; } #ifdef NAN_CHECK ASSERT(machine->Outputs[0][3] != 0.0F); @@ -433,28 +433,28 @@ run_vp( struct gl_context *ctx, struct tnl_pipeline_stage *stage ) /* Setup the VB pointers so that the next pipeline stages get * their data from the right place (the program output arrays). */ - VB->ClipPtr = &store->results[VERT_RESULT_HPOS]; + VB->ClipPtr = &store->results[VARYING_SLOT_POS]; VB->ClipPtr->size = 4; VB->ClipPtr->count = VB->Count; } - VB->AttribPtr[VERT_ATTRIB_COLOR0] = &store->results[VERT_RESULT_COL0]; - VB->AttribPtr[VERT_ATTRIB_COLOR1] = &store->results[VERT_RESULT_COL1]; - VB->AttribPtr[VERT_ATTRIB_FOG] = &store->results[VERT_RESULT_FOGC]; - VB->AttribPtr[_TNL_ATTRIB_POINTSIZE] = &store->results[VERT_RESULT_PSIZ]; - VB->BackfaceColorPtr = &store->results[VERT_RESULT_BFC0]; - VB->BackfaceSecondaryColorPtr = &store->results[VERT_RESULT_BFC1]; + VB->AttribPtr[VERT_ATTRIB_COLOR0] = &store->results[VARYING_SLOT_COL0]; + VB->AttribPtr[VERT_ATTRIB_COLOR1] = &store->results[VARYING_SLOT_COL1]; + VB->AttribPtr[VERT_ATTRIB_FOG] = &store->results[VARYING_SLOT_FOGC]; + VB->AttribPtr[_TNL_ATTRIB_POINTSIZE] = &store->results[VARYING_SLOT_PSIZ]; + VB->BackfaceColorPtr = &store->results[VARYING_SLOT_BFC0]; + VB->BackfaceSecondaryColorPtr = &store->results[VARYING_SLOT_BFC1]; for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) { VB->AttribPtr[_TNL_ATTRIB_TEX0 + i] - = &store->results[VERT_RESULT_TEX0 + i]; + = &store->results[VARYING_SLOT_TEX0 + i]; } for (i = 0; i < ctx->Const.MaxVarying; i++) { - if (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_VAR0 + i)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(VARYING_SLOT_VAR0 + i)) { /* Note: varying results get put into the generic attributes */ VB->AttribPtr[VERT_ATTRIB_GENERIC0+i] - = &store->results[VERT_RESULT_VAR0 + i]; + = &store->results[VARYING_SLOT_VAR0 + i]; } } @@ -502,7 +502,7 @@ dtr(struct tnl_pipeline_stage *stage) GLuint i; /* free the vertex program result arrays */ - for (i = 0; i < VERT_RESULT_MAX; i++) + for (i = 0; i < VARYING_SLOT_MAX; i++) _mesa_vector4f_free( &store->results[i] ); /* free misc arrays */ |