diff options
| author | Gert Wollny <[email protected]> | 2018-05-26 18:48:32 +0200 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-05-28 02:57:46 +0100 |
| commit | 1aec4a07d45164fdb9ba4bc97f330a0e217e3bef (patch) | |
| tree | acb68d1d33dc85f71f3ba33c14b6abf35e088b6f /src | |
| parent | 42cd2810aa30dfd825d46a305134fbc8f239247c (diff) | |
r600: Fix SSG when not all components are written
Make sure only those components are written to that are specified in the
write mask.
Fixes:
dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_vertex
dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_vertex
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_vertex
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_vertex
dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_vertex
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_vertex
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_fragment
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/r600/r600_shader.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index da89bb28e7a..c9f2fa64854 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -6679,11 +6679,15 @@ static int tgsi_issg(struct r600_shader_ctx *ctx) static int tgsi_ssg(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; + unsigned write_mask = inst->Dst[0].Register.WriteMask; + int last_inst = tgsi_last_instruction(write_mask); struct r600_bytecode_alu alu; int i, r; /* tmp = (src > 0 ? 1 : src) */ - for (i = 0; i < 4; i++) { + for (i = 0; i <= last_inst; i++) { + if (!(write_mask & (1 << i))) + continue; memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP3_CNDGT; alu.is_op3 = 1; @@ -6695,7 +6699,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx) alu.src[1].sel = V_SQ_ALU_SRC_1; r600_bytecode_src(&alu.src[2], &ctx->src[0], i); - if (i == 3) + if (i == last_inst) alu.last = 1; r = r600_bytecode_add_alu(ctx->bc, &alu); if (r) @@ -6703,7 +6707,9 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx) } /* dst = (-tmp > 0 ? -1 : tmp) */ - for (i = 0; i < 4; i++) { + for (i = 0; i <= last_inst; i++) { + if (!(write_mask & (1 << i))) + continue; memset(&alu, 0, sizeof(struct r600_bytecode_alu)); alu.op = ALU_OP3_CNDGT; alu.is_op3 = 1; @@ -6719,7 +6725,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx) alu.src[2].sel = ctx->temp_reg; alu.src[2].chan = i; - if (i == 3) + if (i == last_inst) alu.last = 1; r = r600_bytecode_add_alu(ctx->bc, &alu); if (r) |