diff options
| author | Chad Versace <[email protected]> | 2012-01-17 15:41:46 -0800 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2012-01-17 17:26:45 -0800 |
| commit | a6dd4bf5fcce2520ab199201fdd1ad155457d781 (patch) | |
| tree | 8eebc2c9d00d0c715e44f92339d52cd78445da80 /src | |
| parent | ce1c949b162260cec84431913f7aac83cb1b938e (diff) | |
i965/gen5: Fix rendering of depth buffers without stencil [v2]
Fixes the following OGLConform tests on gen5:
depth-stencil(misc.state_on.depth_int)
fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender)
The problem was that, if the depth buffer's Mesa format was X8_Z24, then
we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8
must be emitted.
This bug was introduced by:
commit d84a180417d1eabd680554970f1eaaa93abcd41e
Author: Eric Anholt <[email protected]>
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
v2: Deref 'intel' directly. Move the branch for newer chipset to top.
Quote the PRM. As requested by Ken.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Chad Versace <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index b6bca4ba997..8e59a472bac 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -223,10 +223,23 @@ brw_depthbuffer_format(struct brw_context *brw) case MESA_FORMAT_Z32_FLOAT: return BRW_DEPTHFORMAT_D32_FLOAT; case MESA_FORMAT_X8_Z24: - if (intel->gen >= 5) + if (intel->gen >= 6) { return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; - else /* Gen4 doesn't support X8; use S8 instead. */ + } else { + /* Use D24_UNORM_S8, not D24_UNORM_X8. + * + * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM, + * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits + * 3DSTATE_DEPTH_BUFFER.Surface_Format). + * + * However, on Gen5, D24_UNORM_X8 may be used only if separate + * stencil is enabled, and we never enable it. From the Ironlake PRM, + * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable: + * If this field is disabled, the Surface Format of the depth + * buffer cannot be D24_UNORM_X8_UINT. + */ return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; + } case MESA_FORMAT_S8_Z24: return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; case MESA_FORMAT_Z32_FLOAT_X24S8: |