diff options
author | Paul Berry <[email protected]> | 2013-09-02 08:43:02 -0700 |
---|---|---|
committer | Paul Berry <[email protected]> | 2013-09-16 12:53:21 -0700 |
commit | d5b4095356566b33a1c0a8163099d878fe83822a (patch) | |
tree | 53dba6d1e16cdb08679d034aeea46e6a71ac1bdd /src | |
parent | 8c2b9bd1dfd482622260acbbc122bbfc8bd3bbf9 (diff) |
i965/sf: Use BRW_SF_URB_ENTRY_READ_OFFSET rather than hardcoded values.
We always program the SF unit to start reading the vertex URB entry at
offset 1. In upcoming patches, we'll be adding FS code that relies on
this. So consistently use the constant BRW_SF_URB_ENTRY_READ_OFFSET
rather than hardcoding a 1.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 10 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_sf.h | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_sf_state.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen7_sf_state.c | 2 |
4 files changed, 12 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index b9c9f505fe0..4c6bedc0629 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -478,6 +478,16 @@ struct brw_sf_prog_data { GLuint urb_entry_size; }; + +/** + * We always program SF to start reading at an offset of 1 (2 varying slots) + * from the start of the vertex URB entry. This causes it to skip: + * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5 + * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+ + */ +#define BRW_SF_URB_ENTRY_READ_OFFSET 1 + + struct brw_clip_prog_data { GLuint curb_read_length; /* user planes? */ GLuint clip_mode; diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h index 09880fe2bb3..00062396bd7 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.h +++ b/src/mesa/drivers/dri/i965/brw_sf.h @@ -105,6 +105,4 @@ void brw_emit_point_setup( struct brw_sf_compile *c, bool allocate ); void brw_emit_point_sprite_setup( struct brw_sf_compile *c, bool allocate ); void brw_emit_anyprim_setup( struct brw_sf_compile *c ); -#define BRW_SF_URB_ENTRY_READ_OFFSET 1 - #endif diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c index c76debeff30..dfe9a31a738 100644 --- a/src/mesa/drivers/dri/i965/gen6_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c @@ -138,7 +138,7 @@ upload_sf_state(struct brw_context *brw) bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1; int attr = 0, input_index = 0; - int urb_entry_read_offset = 1; + const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET; float point_size; uint16_t attr_overrides[VARYING_SLOT_MAX]; uint32_t point_sprite_origin; diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index 0ff33888c79..715eb6ccb12 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -40,7 +40,7 @@ upload_sbe_state(struct brw_context *brw) uint32_t dw1, dw10, dw11; int i; int attr = 0, input_index = 0; - int urb_entry_read_offset = 1; + const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET; uint16_t attr_overrides[VARYING_SLOT_MAX]; /* _NEW_BUFFERS */ bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); |