i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcode

This opcode will be used when sending SVB WRITE messages to save
transform feedback outputs into Streamed Vertex Buffers.

Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]>
Acked-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>

4 files changed, 63 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e359c4509b7..1fe4bb57c5a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1043,6 +1043,18 @@ enum opcode {
     * - dst is the GRF where PrimitiveID information will be moved.
     */
    GS_OPCODE_SET_PRIMITIVE_ID,
+
+   /**
+    * Write transform feedback data to the SVB by sending a SVB WRITE message.
+    * Used in gen6.
+    *
+    * - dst is the MRF register containing the message header.
+    *
+    * - src0 is the register where the vertex data is going to be copied from.
+    *
+    * - src1 is the destination register when write commit occurs.
+    */
+   GS_OPCODE_SVB_WRITE,
 };
 
 enum brw_derivative_quality {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index e4c39487882..45e126f98c0 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -528,6 +528,8 @@ brw_instruction_name(enum opcode op)
       return "ff_sync";
    case GS_OPCODE_SET_PRIMITIVE_ID:
       return "set_primitive_id";
+   case GS_OPCODE_SVB_WRITE:
+      return "gs_svb_write";
 
    default:
       /* Yes, this leaks.  It's in debug code, it should never occur, and if
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index f2ec26a566f..8391319517c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -220,6 +220,9 @@ public:
    enum brw_urb_write_flags urb_write_flags;
    bool header_present;
 
+   unsigned sol_binding; /**< gen6: SOL binding table index */
+   bool sol_final_write; /**< gen6: send commit message */
+
    bool is_send_from_grf();
    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
    void reswizzle(int dst_writemask, int swizzle);
@@ -654,6 +657,10 @@ private:
                                      struct brw_reg src1);
    void generate_gs_set_vertex_count(struct brw_reg dst,
                                      struct brw_reg src);
+   void generate_gs_svb_write(vec4_instruction *inst,
+                              struct brw_reg dst,
+                              struct brw_reg src0,
+                              struct brw_reg src1);
    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
    void generate_gs_prepare_channel_masks(struct brw_reg dst);
    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index c2d0d2ecbed..db936206aa2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -574,6 +574,44 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
 }
 
 void
+vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
+                                      struct brw_reg dst,
+                                      struct brw_reg src0,
+                                      struct brw_reg src1)
+{
+   int binding = inst->sol_binding;
+   bool final_write = inst->sol_final_write;
+
+   brw_push_insn_state(p);
+   /* Copy Vertex data into M0.x */
+   brw_MOV(p, stride(dst, 4, 4, 1),
+           stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
+
+   /* Send SVB Write */
+   brw_svb_write(p,
+                 final_write ? src1 : brw_null_reg(), /* dest == src1 */
+                 1, /* msg_reg_nr */
+                 dst, /* src0 == previous dst */
+                 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
+                 final_write); /* send_commit_msg */
+
+   /* Finally, wait for the write commit to occur so that we can proceed to
+    * other things safely.
+    *
+    * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
+    *
+    *   The write commit does not modify the destination register, but
+    *   merely clears the dependency associated with the destination
+    *   register. Thus, a simple “mov” instruction using the register as a
+    *   source is sufficient to wait for the write commit to occur.
+    */
+   if (final_write) {
+      brw_MOV(p, src1, src1);
+   }
+   brw_pop_insn_state(p);
+}
+
+void
 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
 {
    brw_push_insn_state(p);
@@ -1347,6 +1385,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
          generate_gs_urb_write_allocate(inst);
          break;
 
+      case GS_OPCODE_SVB_WRITE:
+         generate_gs_svb_write(inst, dst, src[0], src[1]);
+         break;
+
       case GS_OPCODE_THREAD_END:
          generate_gs_thread_end(inst);
          break;