diff options
author | Daniel Vetter <[email protected]> | 2010-12-01 20:59:45 +0100 |
---|---|---|
committer | Jakob Bornecrantz <[email protected]> | 2010-12-02 01:34:13 +0100 |
commit | a95e694eaf3b40c86fbe8116fc3b5f1add365898 (patch) | |
tree | 91041279c61c9f826cae7191faa2d20787c3ac46 /src | |
parent | 2ff0879a6365e7f7d7e5277274bc965ad57a82b4 (diff) |
i915g: implement unfenced color&depth buffer using tiling bits
v2: Clarify tiling bit calculation as suggested by Chris Wilson.
Signed-off-by: Daniel Vetter <[email protected]>
Reviewed-by: Jakob Bornecrantz <[email protected]>
Signed-off-by: Jakob Bornecrantz <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/gallium/drivers/i915/i915_context.h | 3 | ||||
-rw-r--r-- | src/gallium/drivers/i915/i915_state_emit.c | 27 |
2 files changed, 22 insertions, 8 deletions
diff --git a/src/gallium/drivers/i915/i915_context.h b/src/gallium/drivers/i915/i915_context.h index 3ae61d0ea70..7103a1b8c16 100644 --- a/src/gallium/drivers/i915/i915_context.h +++ b/src/gallium/drivers/i915/i915_context.h @@ -193,8 +193,7 @@ struct i915_velems_state { }; -struct i915_context -{ +struct i915_context { struct pipe_context base; struct i915_winsys *iws; diff --git a/src/gallium/drivers/i915/i915_state_emit.c b/src/gallium/drivers/i915/i915_state_emit.c index 51bbb2bb08e..803cc902854 100644 --- a/src/gallium/drivers/i915/i915_state_emit.c +++ b/src/gallium/drivers/i915/i915_state_emit.c @@ -86,6 +86,22 @@ framebuffer_size(const struct pipe_framebuffer_state *fb, } } +static inline uint32_t +buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) +{ + uint32_t tiling_bits = 0; + + switch (tiling) { + case I915_TILE_Y: + tiling_bits |= BUF_3D_TILE_WALK_Y; + case I915_TILE_X: + tiling_bits |= BUF_3D_TILED_SURFACE; + case I915_TILE_NONE: + break; + } + + return tiling_bits; +} /* Push the state into the sarea and/or texture memory. */ @@ -220,17 +236,17 @@ i915_emit_hardware_state(struct i915_context *i915 ) struct pipe_surface *depth_surface = i915->framebuffer.zsbuf; if (cbuf_surface) { - unsigned ctile = BUF_3D_USE_FENCE; struct i915_texture *tex = i915_texture(cbuf_surface->texture); + uint32_t tiling_bits = 0; assert(tex); OUT_BATCH(_3DSTATE_BUF_INFO_CMD); OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(tex->stride) | /* pitch in bytes */ - ctile); + buf_3d_tiling_bits(tex->tiling)); - OUT_RELOC_FENCED(tex->buffer, + OUT_RELOC(tex->buffer, I915_USAGE_RENDER, cbuf_surface->offset); } @@ -238,7 +254,6 @@ i915_emit_hardware_state(struct i915_context *i915 ) /* What happens if no zbuf?? */ if (depth_surface) { - unsigned ztile = BUF_3D_USE_FENCE; struct i915_texture *tex = i915_texture(depth_surface->texture); assert(tex); @@ -247,9 +262,9 @@ i915_emit_hardware_state(struct i915_context *i915 ) assert(tex); OUT_BATCH(BUF_3D_ID_DEPTH | BUF_3D_PITCH(tex->stride) | /* pitch in bytes */ - ztile); + buf_3d_tiling_bits(tex->tiling)); - OUT_RELOC_FENCED(tex->buffer, + OUT_RELOC(tex->buffer, I915_USAGE_RENDER, depth_surface->offset); } |