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authorKenneth Graunke <[email protected]>2013-05-15 21:18:28 -0700
committerKenneth Graunke <[email protected]>2013-05-20 13:03:17 -0700
commit92d2f5acfadea672417b6785710c9e8b7f605e41 (patch)
tree8edfd48ad341bda27e1a20a5269bb545a1db3c28 /src
parent50e60bf8daabc473ab7caa23bb60cff8c2954d6f (diff)
i965: Require hardware contexts (and thus Kernel 3.6) on Gen6+.
Hardware contexts are necessary to reasonably support OpenGL 3.2. In particular, we currently maintain software counters for transform feedback buffer offsets and counters, which relies on knowing the number of primitives generated. Geometry shaders violate that assumption. At the time of writing, Debian has moved to Kernel 3.8, which means most people probably have a newer kernel by now. It's also worth noting that this patch won't land until Mesa 10 which is currently targeted for September. By that point, even more people will have a newer kernel. Also, don't bother trying to allocate contexts on pre-Gen6, as it currently will always fail, and if this changes in the future, we'll need to reevaluate our hw_ctx/gen checks. This patch leaves the code for flagging BRW_NEW_CONTEXT on new batchbuffers if hw_ctx == NULL since that still occurs pre-Gen6. Also remove the Gen7+ check for kernel 3.3, since it's now redundant. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c18
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c7
2 files changed, 17 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 69b7e4dead8..2f5fedbbb49 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -143,6 +143,23 @@ brwCreateContext(int api,
return false;
}
+ if (intel->gen >= 6) {
+ /* Create a new hardware context. Using a hardware context means that
+ * our GPU state will be saved/restored on context switch, allowing us
+ * to assume that the GPU is in the same state we left it in.
+ *
+ * This is required for transform feedback buffer offsets, query objects,
+ * and also allows us to reduce how much state we have to emit.
+ */
+ intel->hw_ctx = drm_intel_gem_context_create(intel->bufmgr);
+
+ if (!intel->hw_ctx) {
+ fprintf(stderr, "Gen6+ requires Kernel 3.6 or later.\n");
+ ralloc_free(brw);
+ return false;
+ }
+ }
+
brw_init_surface_formats(brw);
/* Initialize swrast, tnl driver tables: */
@@ -374,7 +391,6 @@ brwCreateContext(int api,
brw->prim_restart.in_progress = false;
brw->prim_restart.enable_cut_index = false;
- intel->hw_ctx = drm_intel_gem_context_create(intel->bufmgr);
brw_init_state( brw );
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 433f4ed2bd3..325304d266d 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -1301,13 +1301,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
intelScreen->gen = 2;
}
- if (intelScreen->gen == 7 &&
- !intel_get_boolean(intelScreen->driScrnPriv,
- I915_PARAM_HAS_GEN7_SOL_RESET)) {
- fprintf(stderr, "i965 requires Kernel 3.3 or later.\n");
- return false;
- }
-
intelScreen->hw_has_separate_stencil = intelScreen->gen >= 6;
intelScreen->hw_must_use_separate_stencil = intelScreen->gen >= 7;