gallium/radeon: Fix r300g tiling breakage.

Commit 11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 broke the r300g build. Fix it
up, and reinstate some code which isn't needed by r600g and radeonsi but is
by r300g.

6 files changed, 18 insertions, 3 deletions

diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 812fe39155a..e025c2fcd1e 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -713,6 +713,7 @@ static void r300_tex_set_tiling_flags(struct r300_context *r300,
         tex->tex.macrotile[level]) {
         r300->rws->buffer_set_tiling(tex->buf, r300->cs,
                 tex->tex.microtile, tex->tex.macrotile[level],
+                0, 0, 0, 0, 0,
                 tex->tex.stride_in_bytes[0]);
 
         tex->surface_level = level;
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index c9af04fac5d..6901722f6c1 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -917,6 +917,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
 
     rws->buffer_set_tiling(tex->buf, NULL,
             tex->tex.microtile, tex->tex.macrotile[0],
+            0, 0, 0, 0, 0,
             tex->tex.stride_in_bytes[0]);
 
     return tex;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 7a55d8e9d05..d6f85c38c32 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -451,6 +451,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
 
 	rscreen->ws->buffer_set_tiling(resource->buf,
+				       NULL,
 				       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
 				       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
 				       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c
index 80d5c7c0ee3..8a62d68ff86 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -461,6 +461,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
 
 	rscreen->ws->buffer_set_tiling(resource->buf,
+				       NULL,
 				       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
 				       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
 				       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 86d35c19de6..2626586afd6 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -684,6 +684,7 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 }
 
 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
+                                 struct radeon_winsys_cs *rcs,
                                  enum radeon_bo_layout microtiled,
                                  enum radeon_bo_layout macrotiled,
                                  unsigned bankw, unsigned bankh,
@@ -693,10 +694,17 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
                                  uint32_t pitch)
 {
     struct radeon_bo *bo = get_radeon_bo(_buf);
+    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
     struct drm_radeon_gem_set_tiling args;
 
     memset(&args, 0, sizeof(args));
 
+    /* Tiling determines how DRM treats the buffer data.
+     * We must flush CS when changing it if the buffer is referenced. */
+    if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
+        cs->flush_cs(cs->flush_data, 0);
+    }
+
     while (p_atomic_read(&bo->num_active_ioctls)) {
         sched_yield();
     }
@@ -713,9 +721,11 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
         RADEON_TILING_EG_BANKW_SHIFT;
     args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
         RADEON_TILING_EG_BANKH_SHIFT;
-    args.tiling_flags |= (eg_tile_split_rev(tile_split) &
-			  RADEON_TILING_EG_TILE_SPLIT_MASK) <<
-        RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+    if (tile_split) {
+	args.tiling_flags |= (eg_tile_split_rev(tile_split) &
+			      RADEON_TILING_EG_TILE_SPLIT_MASK) <<
+	    RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+    }
     args.tiling_flags |= (stencil_tile_split &
 			  RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
         RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 443b20e25b9..73160b63a27 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -219,6 +219,7 @@ struct radeon_winsys {
      * \note microtile and macrotile are not bitmasks!
      */
     void (*buffer_set_tiling)(struct pb_buffer *buf,
+                              struct radeon_winsys_cs *rcs,
                               enum radeon_bo_layout microtile,
                               enum radeon_bo_layout macrotile,
                               unsigned bankw, unsigned bankh,