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authorTom Stellard <thomas.stellard@amd.com>2012-05-24 09:01:33 -0400
committerTom Stellard <thomas.stellard@amd.com>2012-05-24 14:12:32 -0400
commit662ccbfc21a650e0a52f6d293fa33f9e23e654c6 (patch)
tree54d07178208a04b78c5f4a45e243af46ace1d113 /src
parent177b420283547e472632bc650f218ad4b0b541d5 (diff)
radeon/llvm: Remove AMDIL instructions MULHI, SMUL
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl2
-rw-r--r--src/gallium/drivers/radeon/AMDILInstructions.td3
-rw-r--r--src/gallium/drivers/radeon/R600Instructions.td10
3 files changed, 5 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index 7192accadfa..a77126d7110 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -44,7 +44,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'SMULHI_i32', 'SMUL_i32', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
while (<AMDIL>) {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index cb31bddf11e..4907cc53561 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -51,8 +51,6 @@ def INTTOANY_i16: OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins GPRI32:$src0),
// Signed 32bit integer math instructions start here
//===---------------------------------------------------------------------===//
defm NEGATE : UnaryOpMCi32<IL_OP_I_NEGATE, IL_inegate>;
-defm SMUL : BinaryOpMCi32<IL_OP_I_MUL, mul>;
-defm SMULHI : BinaryOpMCi32<IL_OP_I_MUL_HIGH, mulhs>;
// get rid of the addri via the tablegen instead of custom lowered instruction
defm EADD : BinaryOpMCi32<IL_OP_I_ADD, adde>;
def INTTOANY_i32: OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins GPRI32:$src0),
@@ -113,7 +111,6 @@ def FTOV4U8_i32 : OneInOneOut<IL_OP_F2U4, (outs GPRI32:$dst),
// Unsigned 32bit integer math instructions start here
//===---------------------------------------------------------------------===//
defm UMUL : BinaryOpMCi32<IL_OP_U_MUL, IL_umul>;
-defm UMULHI : BinaryOpMCi32<IL_OP_U_MUL_HIGH, mulhu>;
defm UDIV : BinaryOpMCi32<IL_OP_U_DIV, udiv>;
defm NATIVE_UDIV : BinaryIntrinsicInt<IL_OP_U_DIV, int_AMDIL_udiv>;
let mayLoad=0, mayStore=0 in {
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index a2427769082..7bfd552d86e 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -663,9 +663,8 @@ class ASHR_Common <bits<32> inst> : R600_2OP <
class MULHI_INT_Common <bits<32> inst> : R600_2OP <
inst, "MULHI_INT $dst, $src0, $src1",
- [] >{
- let AMDILOp = AMDILInst.SMULHI_i32;
-}
+ [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
inst, "MULHI $dst, $src0, $src1",
@@ -674,9 +673,8 @@ class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
class MULLO_INT_Common <bits<32> inst> : R600_2OP <
inst, "MULLO_INT $dst, $src0, $src1",
- [] >{
- let AMDILOp = AMDILInst.SMUL_i32;
-}
+ [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
inst, "MULLO_UINT $dst, $src0, $src1",