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authorEric Anholt <[email protected]>2010-10-06 10:22:22 -0700
committerEric Anholt <[email protected]>2010-10-06 12:13:08 -0700
commit5d99b01501128c7179cdd6aa29bc8953d0d81e75 (patch)
treee7c15f4adf06ba1eb19cf244a995cb5d5afd6efb /src
parent5eeaf3671e2f913d38187fd1401c4b22a2900d57 (diff)
i965: Add some clarification of the WECtrl field.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h21
-rw-r--r--src/mesa/drivers/dri/i965/brw_disasm.c4
2 files changed, 21 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index f9c12e15558..9633c95ff50 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -501,9 +501,26 @@
#define BRW_MASK_ENABLE 0
#define BRW_MASK_DISABLE 1
-/* Sandybridge is WECtrl (Write enable control) */
+/** @{
+ *
+ * Gen6 has replaced "mask enable/disable" with WECtrl, which is
+ * effectively the same but much simpler to think about. Now, there
+ * are two contributors ANDed together to whether channels are
+ * executed: The predication on the instruction, and the channel write
+ * enable.
+ */
+/**
+ * This is the default value. It means that a channel's write enable is set
+ * if the per-channel IP is pointing at this instruction.
+ */
#define BRW_WE_NORMAL 0
-#define BRW_WE_KILL_PRED 1
+/**
+ * This is used like BRW_MASK_DISABLE, and causes all channels to have
+ * their write enable set. Note that predication still contributes to
+ * whether the channel actually gets written.
+ */
+#define BRW_WE_ALL 1
+/** @} */
#define BRW_OPCODE_MOV 1
#define BRW_OPCODE_SEL 2
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index be27f9226c3..12b8f2e4678 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -165,8 +165,8 @@ char *accwr[2] = {
};
char *wectrl[2] = {
- [0] = "WEnormal",
- [1] = "WEpredicted"
+ [0] = "WE_normal",
+ [1] = "WE_all"
};
char *exec_size[8] = {