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authorAnuj Phogat <[email protected]>2015-07-29 09:41:18 -0700
committerAnuj Phogat <[email protected]>2015-07-29 14:46:30 -0700
commit2484263fe97cebc9fa7a5c9de04c757dc6cc7713 (patch)
tree8beca0299cc6ae7b2b8589d1cef7652d259c4a0d /src
parent8413822c8cfaf9110625c1a4a66ee916c2a916e3 (diff)
Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()
Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/common/meta_blit.c6
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_reg.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c8
-rw-r--r--src/mesa/main/macros.h11
8 files changed, 15 insertions, 26 deletions
diff --git a/src/mesa/drivers/common/meta_blit.c b/src/mesa/drivers/common/meta_blit.c
index 317a304bebf..71d18de87db 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -82,7 +82,7 @@ setup_glsl_msaa_blit_scaled_shader(struct gl_context *ctx,
y_scale = samples * 0.5;
/* We expect only power of 2 samples in source multisample buffer. */
- assert(samples > 0 && is_power_of_two(samples));
+ assert(samples > 0 && _mesa_is_pow_two(samples));
while (samples >> (shader_offset + 1)) {
shader_offset++;
}
@@ -263,7 +263,7 @@ setup_glsl_msaa_blit_shader(struct gl_context *ctx,
}
/* We expect only power of 2 samples in source multisample buffer. */
- assert(samples > 0 && is_power_of_two(samples));
+ assert(samples > 0 && _mesa_is_pow_two(samples));
while (samples >> (shader_offset + 1)) {
shader_offset++;
}
@@ -434,7 +434,7 @@ setup_glsl_msaa_blit_shader(struct gl_context *ctx,
* (so the floating point exponent just gets increased), rather than
* doing a naive sum and dividing.
*/
- assert(is_power_of_two(samples));
+ assert(_mesa_is_pow_two(samples));
/* Fetch each individual sample. */
sample_resolve = rzalloc_size(mem_ctx, 1);
for (i = 0; i < samples; i++) {
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index aef5ff99eb2..f653f441ad8 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -342,7 +342,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
* Thus, I guess we need do this for other platforms as well.
*/
if (tObj->Target == GL_TEXTURE_CUBE_MAP_ARB &&
- !is_power_of_two(firstImage->Height))
+ !_mesa_is_pow_two(firstImage->Height))
return false;
state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */
diff --git a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp
index 01d3a569858..96d4f375da2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp
@@ -173,7 +173,7 @@ ir_vector_reference_visitor::visit_enter(ir_assignment *ir)
return visit_continue_with_parent;
}
if (ir->lhs->as_dereference_variable() &&
- is_power_of_two(ir->write_mask) &&
+ _mesa_is_pow_two(ir->write_mask) &&
!ir->condition) {
/* If we're writing just a channel, then channel-splitting the LHS is OK.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h
index c8b134103bb..4867148c12f 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -853,7 +853,7 @@ static inline struct brw_reg
spread(struct brw_reg reg, unsigned s)
{
if (s) {
- assert(is_power_of_two(s));
+ assert(_mesa_is_pow_two(s));
if (reg.hstride)
reg.hstride += cvt(s) - 1;
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 85c0864d2c8..fb78b08b649 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -63,7 +63,7 @@ tr_mode_horizontal_texture_alignment(const struct brw_context *brw,
int i = 0;
/* Alignment computations below assume bpp >= 8 and a power of 2. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp));
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
switch(mt->target) {
case GL_TEXTURE_1D:
@@ -95,7 +95,7 @@ tr_mode_horizontal_texture_alignment(const struct brw_context *brw,
ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_yf[i] : align_ys[i];
- assert(is_power_of_two(mt->num_samples));
+ assert(_mesa_is_pow_two(mt->num_samples));
switch (mt->num_samples) {
case 2:
@@ -199,7 +199,7 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw,
mt->target != GL_TEXTURE_1D_ARRAY);
/* Alignment computations below assume bpp >= 8 and a power of 2. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)) ;
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ;
switch(mt->target) {
case GL_TEXTURE_2D:
@@ -226,7 +226,7 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw,
ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_yf[i] : align_ys[i];
- assert(is_power_of_two(mt->num_samples));
+ assert(_mesa_is_pow_two(mt->num_samples));
switch (mt->num_samples) {
case 4:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 0483afc8fe0..92050b94d33 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1545,7 +1545,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
*
* where they pack the four bytes from the low and high four DW.
*/
- assert(is_power_of_two(dst.dw1.bits.writemask) &&
+ assert(_mesa_is_pow_two(dst.dw1.bits.writemask) &&
dst.dw1.bits.writemask != 0);
unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 4fc3fa803cb..6d92580e725 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -121,14 +121,14 @@ get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
return 0;
/* Compute array index. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp));
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
i = ffs(bpp / 8) - 1;
align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_2d_yf[i] :
4 * align_2d_yf[i];
- assert(is_power_of_two(align));
+ assert(_mesa_is_pow_two(align));
/* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
if (align == 16)
@@ -150,14 +150,14 @@ get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
return 0;
/* Compute array index. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp));
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
i = ffs(bpp / 8) - 1;
align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_2d_yf[i] :
4 * align_2d_yf[i];
- assert(is_power_of_two(align));
+ assert(_mesa_is_pow_two(align));
/* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
if (align == 16 || align == 32)
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 0608650aeb4..07919a6e1e4 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -679,17 +679,6 @@ minify(unsigned value, unsigned levels)
}
/**
- * Return true if the given value is a power of two.
- *
- * Note that this considers 0 a power of two.
- */
-static inline bool
-is_power_of_two(unsigned value)
-{
- return (value & (value - 1)) == 0;
-}
-
-/**
* Align a value up to an alignment value
*
* If \c value is not already aligned to the requested alignment value, it