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authorEric Anholt <[email protected]>2011-08-05 19:18:31 -0700
committerEric Anholt <[email protected]>2011-08-16 13:04:42 -0700
commiteca762d831e099b549dafa0be896eac82b3fceb9 (patch)
treef251f531789dc93f80889343e727e41d3b14b4b9 /src
parent164ccd27787e0df4ae6f85a7178aff0720d56ac9 (diff)
i965/vs: Fix support for zero uniforms in use.
We were looking for attributes in the wrong place, and pointlessly doing the work on gen6 at all.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_emit.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 1f2853e1118..be089369bcf 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -94,7 +94,7 @@ vec4_visitor::setup_uniforms(int reg)
/* The pre-gen6 VS requires that some push constants get loaded no
* matter what, or the GPU would hang.
*/
- if (this->uniforms == 0) {
+ if (intel->gen < 6 && this->uniforms == 0) {
this->uniform_size[this->uniforms] = 1;
for (unsigned int i = 0; i < 4; i++) {
@@ -105,6 +105,7 @@ vec4_visitor::setup_uniforms(int reg)
}
this->uniforms++;
+ reg++;
} else {
reg += ALIGN(uniforms, 2) / 2;
}