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authorJason Ekstrand <[email protected]>2018-05-29 15:28:36 -0700
committerJason Ekstrand <[email protected]>2018-06-04 14:03:03 -0700
commitdb9675f5a4c68e39bb777eb7003f01854fd235dc (patch)
tree9a39c38fc3f504fbae077d10c56815c6b2d8296d /src
parent2d20303e1874a862117f526ee87789b00b049078 (diff)
intel/eu: Set flag [sub]register number differently for 3src
Prior to gen8, the flag [sub]register number is in a different spot on 3src instructions than on other instructions. Starting with Broadwell, they made it consistent. This commit fixes bugs that occur when a conditional modifier gets propagated into a 3src instruction such as a MAD. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_eu_emit.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index a660d9eaaa5..412a051bc93 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -701,9 +701,16 @@ brw_inst_set_state(const struct gen_device_info *devinfo,
brw_inst_set_pred_control(devinfo, insn, state->predicate);
brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
- brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
- if (devinfo->gen >= 7)
- brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+ if (is_3src(devinfo, brw_inst_opcode(devinfo, insn)) &&
+ state->access_mode == BRW_ALIGN_16) {
+ brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
+ if (devinfo->gen >= 7)
+ brw_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+ } else {
+ brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
+ if (devinfo->gen >= 7)
+ brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+ }
if (devinfo->gen >= 6)
brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control);