diff options
| author | Eric Anholt <[email protected]> | 2017-10-24 19:10:37 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2017-10-30 13:31:16 -0700 |
| commit | d0f7053369920cb4a1d0982b7869ff0577fef961 (patch) | |
| tree | a9b6e5e97623fe81d4759a5c06e8cb79769edcac /src | |
| parent | 40280b0abe46d43ffe669c8094e94c7ac70ab92a (diff) | |
broadcom/xml: Fix address packing for address with >= 8 alignment bits.
We were handing the intra-byte padding fine, but with a 24-bit address
(bottom 8 bits implied 0) we would end up off by 8 bytes in our shift,
impacting vc5's load/store general packets (all other packets we have had
<8 bits of padding).
Diffstat (limited to 'src')
| -rw-r--r-- | src/broadcom/cle/gen_pack_header.py | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/broadcom/cle/gen_pack_header.py b/src/broadcom/cle/gen_pack_header.py index d458c2b1c40..78ad9ad31a4 100644 --- a/src/broadcom/cle/gen_pack_header.py +++ b/src/broadcom/cle/gen_pack_header.py @@ -279,11 +279,13 @@ class Group(object): field_byte_start = (field.start // 8) * 8 start -= field_byte_start end -= field_byte_start + extra_shift = 0 if field.type == "mbo": s = "__gen_mbo(%d, %d)" % \ (start, end) elif field.type == "address": + extra_shift = (31 - (end - start)) // 8 * 8 s = "__gen_address_offset(&values->%s)" % byte.address.name elif field.type == "uint": s = "__gen_uint(values->%s, %d, %d)" % \ @@ -317,8 +319,9 @@ class Group(object): s = None if not s == None: - if byte_start - field_byte_start != 0: - s = "%s >> %d" % (s, byte_start - field_byte_start) + shift = byte_start - field_byte_start + extra_shift + if shift: + s = "%s >> %d" % (s, shift) if field == byte.fields[-1]: print("%s %s;" % (prefix, s)) |