diff options
| author | Kenneth Graunke <[email protected]> | 2017-05-23 21:33:12 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-05-30 14:59:31 -0700 |
| commit | 56535959fd5acf1066506d6387adb16d86d4c65c (patch) | |
| tree | 459b40677644a6946d73223fb8623452e4974bd0 /src | |
| parent | 53368b008e62ddfbda896b5f0d3c69415052a845 (diff) | |
anv: Port over CACHE_MODE_1 optimization fix enables from brw.
Ben and I haven't observed these to help anything, but they enable
hardware optimizations for particular cases. It's probably best to
enable them ahead of time, before we run into such a case.
Reviewed-by: Plamena Manolova <[email protected]>
Acked-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index bf1217bbcdc..00c4105a825 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -52,6 +52,19 @@ genX(init_device_state)(struct anv_device *device) ps.PipelineSelection = _3D; } +#if GEN_GEN >= 9 + uint32_t cache_mode_1; + anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), + .PartialResolveDisableInVC = true, + .PartialResolveDisableInVCMask = true, + .FloatBlendOptimizationEnable = true, + .FloatBlendOptimizationEnableMask = true); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(CACHE_MODE_1_num); + lri.DataDWord = cache_mode_1; + } +#endif + anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa); anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { |