radeon/llvm: Remove AMDGPULowerShaderInstructions class

It is no longer used.

6 files changed, 4 insertions, 86 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index aa590350dea..babcf6e8a4c 100644
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -33,7 +33,6 @@ namespace llvm {
     FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
 
     FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm);
-    FunctionPass *createAMDGPULowerShaderInstructionsPass(TargetMachine &tm);
 
     FunctionPass *createAMDGPUDelimitInstGroupsPass(TargetMachine &tm);
 
diff --git a/src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.cpp b/src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.cpp
deleted file mode 100644
index d33055ccb87..00000000000
--- a/src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.cpp
+++ /dev/null
@@ -1,38 +0,0 @@
-//===-- AMDGPULowerShaderInstructions.cpp - TODO: Add brief description -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-
-#include "AMDGPULowerShaderInstructions.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
-
-using namespace llvm;
-
-void AMDGPULowerShaderInstructionsPass::preloadRegister(MachineFunction * MF,
-    const TargetInstrInfo * TII, unsigned physReg, unsigned virtReg) const
-{
-  if (!MRI->isLiveIn(physReg)) {
-    MRI->addLiveIn(physReg, virtReg);
-    MachineBasicBlock &EntryMBB = MF->front();
-    BuildMI(MF->front(), EntryMBB.begin(), DebugLoc(), TII->get(TargetOpcode::COPY),
-            virtReg)
-            .addReg(physReg);
-  } else {
-    /* We can't mark the same register as preloaded twice, but we still must
-     * associate virtReg with the correct preloaded register. */
-    unsigned newReg = MRI->getLiveInVirtReg(physReg);
-    MRI->replaceRegWith(virtReg, newReg);
-  }
-}
diff --git a/src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.h b/src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.h
deleted file mode 100644
index 5ee77fafe2b..00000000000
--- a/src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.h
+++ /dev/null
@@ -1,40 +0,0 @@
-//===-- AMDGPULowerShaderInstructions.h - TODO: Add brief description -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-
-#ifndef AMDGPU_LOWER_SHADER_INSTRUCTIONS
-#define AMDGPU_LOWER_SHADER_INSTRUCTIONS
-
-namespace llvm {
-
-class MachineFunction;
-class MachineRegisterInfo;
-class TargetInstrInfo;
-
-class AMDGPULowerShaderInstructionsPass {
-
-  protected:
-    MachineRegisterInfo * MRI;
-    /**
-     * @param physReg The physical register that will be preloaded.
-     * @param virtReg The virtual register that currently holds the
-     *                preloaded value.
-     */
-    void preloadRegister(MachineFunction * MF, const TargetInstrInfo * TII,
-                         unsigned physReg, unsigned virtReg) const;
-};
-
-} // end namespace llvm
-
-
-#endif // AMDGPU_LOWER_SHADER_INSTRUCTIONS
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 9149cf3caf5..43aa1e119b3 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -42,7 +42,6 @@ CPP_SOURCES := \
 	AMDGPUISelLowering.cpp		\
 	AMDGPUConvertToISA.cpp		\
 	AMDGPULowerInstructions.cpp		\
-	AMDGPULowerShaderInstructions.cpp	\
 	AMDGPUInstrInfo.cpp		\
 	AMDGPURegisterInfo.cpp		\
 	AMDGPUUtil.cpp			\
diff --git a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
index 808f08c67ef..58b1f0824d7 100644
--- a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
@@ -12,7 +12,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
-#include "AMDGPULowerShaderInstructions.h"
 #include "AMDGPUUtil.h"
 #include "AMDIL.h"
 #include "AMDILInstrInfo.h"
@@ -23,12 +22,12 @@
 using namespace llvm;
 
 namespace {
-  class R600LowerShaderInstructionsPass : public MachineFunctionPass,
-        public AMDGPULowerShaderInstructionsPass {
+  class R600LowerShaderInstructionsPass : public MachineFunctionPass {
 
   private:
     static char ID;
     TargetMachine &TM;
+    MachineRegisterInfo * MRI;
 
     void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
         MachineBasicBlock::iterator I);
diff --git a/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp b/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
index 5d49d88dc7c..d0a2de99b98 100644
--- a/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
+++ b/src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
@@ -13,7 +13,6 @@
 
 
 #include "AMDGPU.h"
-#include "AMDGPULowerShaderInstructions.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -21,12 +20,12 @@
 using namespace llvm;
 
 namespace {
-  class SILowerShaderInstructionsPass : public MachineFunctionPass,
-      public AMDGPULowerShaderInstructionsPass {
+  class SILowerShaderInstructionsPass : public MachineFunctionPass {
 
   private:
     static char ID;
     TargetMachine &TM;
+    MachineRegisterInfo * MRI;
 
   public:
     SILowerShaderInstructionsPass(TargetMachine &tm) :