freedreno/a4xx: add render target format to fd4_emit

This lets us move emitting SP_FS_MRT_REG back to fd4_program_emit.

Signed-off-by: Rob Clark <[email protected]>

5 files changed, 30 insertions, 42 deletions

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
index 2427a8b8a5b..5aaa20b4be6 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
@@ -108,6 +108,7 @@ static void
 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 {
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
+	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 	struct fd4_emit emit = {
 		.vtx  = &ctx->vtx,
 		.prog = &ctx->prog,
@@ -116,7 +117,7 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 			/* do binning pass first: */
 			.binning_pass = true,
 			.color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
-			.alpha = util_format_is_alpha(pipe_surface_format(ctx->framebuffer.cbufs[0])),
+			.alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])),
 			// TODO set .half_precision based on render target format,
 			// ie. float16 and smaller use half, float32 use full..
 			.half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
@@ -128,6 +129,7 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 			.fsaturate_t = fd4_ctx->fsaturate_t,
 			.fsaturate_r = fd4_ctx->fsaturate_r,
 		},
+		.format = fd4_emit_format(pfb->cbufs[0]),
 		.rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 	};
 	unsigned dirty;
@@ -176,6 +178,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers,
 		.key = {
 			.half_precision = true,
 		},
+		.format = fd4_emit_format(pfb->cbufs[0]),
 	};
 	uint32_t colr = 0;
 
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 05f02f64c33..7d04bd5789f 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -453,28 +453,6 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	if (dirty & FD_DIRTY_PROG)
 		fd4_program_emit(ring, emit);
 
-	if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
-		struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-		uint32_t color_regid = ir3_find_output_regid(fp,
-				ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
-		enum a4xx_color_fmt format = 0;
-
-		if (pfb->cbufs[0])
-			format = fd4_pipe2color(pfb->cbufs[0]->format);
-
-		OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid) |
-				A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
-				COND(fp->key.half_precision, A4XX_SP_FS_MRT_REG_HALF_PRECISION));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-		OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	}
-
 	if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
 			/* evil hack to deal sanely with clear path: */
 			(emit->prog == &ctx->prog)) {
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.h b/src/gallium/drivers/freedreno/a4xx/fd4_emit.h
index c5fb24d8d13..d133f011e98 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.h
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.h
@@ -53,6 +53,7 @@ struct fd4_emit {
 	const struct fd_program_stateobj *prog;
 	const struct pipe_draw_info *info;
 	struct ir3_shader_key key;
+	enum a4xx_color_fmt format;
 	uint32_t dirty;
 	bool rasterflat;
 
@@ -61,6 +62,13 @@ struct fd4_emit {
 	/* TODO: other shader stages.. */
 };
 
+static inline enum a4xx_color_fmt fd4_emit_format(struct pipe_surface *surf)
+{
+	if (!surf)
+		return 0;
+	return fd4_pipe2color(surf->format);
+}
+
 static inline struct ir3_shader_variant *
 fd4_emit_get_vp(struct fd4_emit *emit)
 {
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index 05e2df92d46..f3d7b1064dd 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -153,6 +153,7 @@ fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 			.vtx = &fd4_ctx->solid_vbuf_state,
 			.prog = &ctx->solid_prog,
 			.key = key,
+			.format = fd4_emit_format(pfb->cbufs[0]),
 	};
 
 	OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
@@ -242,25 +243,10 @@ fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 /* transfer from system memory to gmem */
 
 static void
-emit_mem2gmem_surf(struct fd_context *ctx, struct fd4_emit *emit,
-		uint32_t base, struct pipe_surface *psurf, uint32_t bin_w)
+emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
+		struct pipe_surface *psurf, uint32_t bin_w)
 {
-	struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
 	struct fd_ringbuffer *ring = ctx->ring;
-	uint32_t color_regid = ir3_find_output_regid(fp,
-			ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
-
-	OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid) |
-			A4XX_SP_FS_MRT_REG_MRTFORMAT(fd4_pipe2color(psurf->format)) |
-			COND(fp->key.half_precision, A4XX_SP_FS_MRT_REG_HALF_PRECISION));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
-	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
 
 	emit_mrt(ring, 1, &psurf, &base, bin_w);
 
@@ -281,6 +267,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 			.vtx = &fd4_ctx->blit_vbuf_state,
 			.prog = &ctx->blit_prog,
 			.key = key,
+			.format = fd4_emit_format(pfb->cbufs[0]),
 	};
 	float x0, y0, x1, y1;
 	unsigned bin_w = tile->bin_w;
@@ -386,10 +373,10 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 	bin_h = gmem->bin_h;
 
 	if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
-		emit_mem2gmem_surf(ctx, &emit, depth_base(ctx), pfb->zsbuf, bin_w);
+		emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
 
 	if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
-		emit_mem2gmem_surf(ctx, &emit, 0, pfb->cbufs[0], bin_w);
+		emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
 
 	OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 	OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
index 66c118fb099..9dbc79c2af9 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_program.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
@@ -383,6 +383,18 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
 		OUT_RING(ring, 0x00000001);
 	}
 
+	OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid) |
+			A4XX_SP_FS_MRT_REG_MRTFORMAT(emit->format) |
+			COND(emit->key.half_precision, A4XX_SP_FS_MRT_REG_HALF_PRECISION));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+	OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(0));
+
 	if (emit->key.binning_pass) {
 		OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
 		OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |